Rail-to-rail delay line for time analog-to-digital converters

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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Details

C341S155000

Reexamination Certificate

active

07106239

ABSTRACT:
A time-analog-to-digital converter (TAD) utilizes a time-to-digital approach for analog-to-digital conversion. The TAD includes two voltage-to-delay converters (VDCs), e.g., CMOS inverter chains, in order to increase the dynamic range of the TAD. Each VDC can handle a different range of input voltages. Comparators compare the input signal voltage to reference voltages corresponding to the different ranges of input voltage and a selector selects one of the VDC line outputs based on the range in which the input signal lies. A filter estimates the input signal voltage from a delay signal from the selected output.

REFERENCES:
patent: 5396247 (1995-03-01), Watanabe et al.
patent: 6653964 (2003-11-01), Mizuno et al.
patent: 6850178 (2005-02-01), Watanabe
patent: 6958721 (2005-10-01), Vincent et al.
Watanabe, Takamot:An All-Digital Analog-to-Digital Converter With 12-μ V/LSB Using Moving-Average Filtering: IEEE Journal of Solid-State Circuits, vol. 38, No. 1 (Jan. 2005)pp. 120-125.
Watanabe, Takamot:An All-Digital PLL for Frequency Multiplication by 4 to 1022 With Seven-Cycle Lock Time: IEEE Journal of Solid-State Circuits, vol. 38, No. 2 (Feb. 2003)pp. 198-204.

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