Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2000-10-03
2003-04-08
Nguyen, Patricia T. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S253000, C330S261000
Reexamination Certificate
active
06545538
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates generally to the field of integrated circuit CMOS operational amplifiers, and more particularly to rail-to-rail class AB output stages for integrated circuit CMOS operational amplifiers, and still more particularly to such operational amplifiers and class AB output stages thereof which (1) are made using a low cost “single well” CMOS manufacturing process wherein large drain-body leakage currents are caused by drain-source voltages of more than approximately 1-2 volts, and (2) are operable both at high and low power supply voltages without nonlinear distortion caused by large leakage currents due to impact ionization.
By way of background, in many applications it is very desirable that an integrated circuit operational amplifier be capable of “rail-to-rail” operation. This means that the output voltage of the operational amplifier, which typically is produced by a class AB output stage, should be able to swing close to the upper power supply voltage and the lower power supply voltage. (The upper power supply voltage can be called V
+
and the lower power supply voltage can be called “ground”.) The closest prior art presently known to the inventors includes U.S Pat. No. 5,311,145 (Huijsing et al.), U.S Pat. No. 4,570,128 (Monticelli), and the article “Design Aspects of Rail-to-Rail CMOS OpAm” by Gierkink, Holzmann, Wiegerink, and Wassenaar, Proceedings of the First VLSI Workshop, May 6-8, 1997, Columbus, Ohio, pp. 23-28.
If rail-to-rail operational amplifiers of the prior art are manufactured using “single well” CMOS processes rather than the more complex and more expensive “double well” processes, then there are large leakage currents due to impact ionization in the MOSFETs when they are subjected to drain-to-source voltages greater than approximately 1-2 volts. The drain-body leakage of an MOS transistor is proportional to the current in the source electrode thereof, and is a highly nonlinear function of the drain-source voltage of the MOS transistor. From a circuit analysis viewpoint, the drain-body leakage current can be thought of as a parasitic nonlinear resistor connected between the drain and body electrodes of a MOSFET. In a class AB output stage, that nonlinear parasitic resistance can become the dominating factor in the equivalent input resistance of the class AB output stage. For a typical “single well” manufacturing process, the drain-body leakage of an MOS transistor is almost negligible when its drain-source voltage is less than 1-2 volts, but the drain-body leakage current rapidly increases for larger drain-source voltages. Therefore, both P-channel and N-channel MOSFETs in a CMOS circuit are likely to have drain-to-body leakage currents that are large enough to impair circuit operation (for example, by reducing the open loop gain of an operational amplifier and by causing nonlinear distortion of an operational amplifier output) if the supply voltage V
DD
is greater than about 3 volts. The drain-source voltage at which the drain-body leakage current becomes significant decreases substantially as the channel length decreases from for example 6.0 microns to 5.5 microns or less. Although this problem could be solved if the transistors of the class AB output stage are placed in separate wells in a “double-well” manufacturing process (with their body electrodes connected to their source electrodes ) typical “double-well” manufacturing processes are usually more than twice as expensive as typical “single-well” manufacturing processes. Since the leakage currents in similar CMOS operational amplifiers manufactured using “single-well” manufacturing processes cause the gains of the operational amplifiers to be reduced as the supply voltage increases, it has not been practical to provide an inexpensive, highly linear, high-speed, rail-to-rail CMOS integrated circuit operational amplifier.
Those skilled in the art know that providing more than two gain stages in an operational amplifier decreases the speed of the operational amplifier. Each additional gain stage beyond two decreases the speed of the operational amplifier by a factor of 2-4. Therefore, there is a difficult trade-off between the objectives of increasing the operating speed of an operational amplifier and increasing its open loop gain by adding gain stages.
Accordingly, there is an unmet need for a high speed integrated circuit CMOS operational amplifier, and a class AB output stage therefor having rail-to-rail operation, wherein the operational amplifier and the class AB output stage are manufactured using low cost single-well CMOS technology, and are operable at high speed without substantial signal instability or signal distortion even at high power supply voltages that normally would cause drain-source voltages large enough to result in substantial drain-body leakage currents in MOSFETs of the class AB output stage.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a class AB rail-to-rail output stage which is stable and linear over a wide range of supply voltages.
It is another object of the invention to provide a class AB rail-to-rail output stage which is stable and linear over a wide range of supply voltages and is manufactured by a low cost single-well CMOS manufacturing process.
It is another object of the invention to provide an inexpensive, stable high speed rail-to-rail operational amplifier having a class AB rail-to-rail output stage, wherein the operational amplifier is linear over a wide range of supply voltages.
It is another object of the invention to provide an inexpensive, stable rail-to-rail operational amplifier having a class AB rail-to-rail output stage, wherein the operational amplifier is linear over a wide range of supply voltages and is manufactured by a low cost single-well CMOS manufacturing process.
It is another object of the invention to provide an inexpensive, high speed, stable rail-to-rail operational amplifier having a class AB rail-to-rail output stage and which avoids. deterioration of amplifier gain as the supply voltage increases.
It is another object of the invention to provide an inexpensive two-stage, high speed operational amplifier having high gain.
It is another object of the invention to provide a very compact, high-performance operational amplifier in a small package.
It is another object of the invention to provide a rail-to-rail class AB output stage having very high equivalent input resistance.
Briefly described, and in accordance with one embodiment thereof, the invention provides a technique for reducing impact ionization in an N-channel MOSFET (
11
) in a CMOS integrated circuit device so as to reduce a drain-to-body leakage current in the MOSFET, including forming the MOSFET in a P-type substrate in a single-well CMOS manufacturing process, coupling a non-inverting input and an inverting input of a servo amplifier (
12
) to a drain of the MOSFET and a reference voltage (
65
), respectively. The servo amplifier is operated to control a drain current in the MOSFET so as to prevent the magnitude of the drain-source voltage of the MOSFET from exceeding a value at which impact ionization causes the drain-to-body leakage current to exceed a predetermined level.
In one embodiment, the invention provides a rail-to-rail class AB output stage including: a P-channel pull-up transistor (
4
) having a source coupled to a first supply rail voltage (V
+
), a gate coupled to a first input conductor (
2
) of the output stage, and a drain coupled to an output terminal (
6
) of the output stage. An N-channel pull-down transistor (
5
) has a source coupled to a second supply rail voltage (GROUND), a gate coupled to a second input conductor (
3
) of the output stage, and a drain coupled to the output terminal (
6
). A P-channel first bias transistor (
10
) includes a source coupled to the first input conductor (
2
), and an N-channel second bias transistor (
11
) has a source coupled to the second input terminal (
3
) and a drain connected to a drain of the first bias transistor (
10
Ivanov Vadim V.
Johnson Gregory H.
Sanchez Stephen J.
Brady W. James
Nguyen Patricia T.
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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