Amplifiers – Combined with automatic amplifier disabling switch means
Reexamination Certificate
2000-11-15
2002-05-07
Pascal, Robert (Department: 2817)
Amplifiers
Combined with automatic amplifier disabling switch means
C330S136000, C330S285000
Reexamination Certificate
active
06384679
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for a rail-to-rail amplifier. In particular, the present invention relates to a method and apparatus that uses a rail-to-rail amplifier with a reduced gain, allowing the compensation network to be reduced in size while maintaining suitable stability over the amplifiers operating voltage range.
BACKGROUND OF THE INVENTION
Differential amplifiers normal only operate over a limited range of input voltages. The maximum input voltage range for which a circuit continues to operate as an amplifier is termed the input common-mode range (CMR). When the input voltages (or common mode voltage) exceed the input CMR, transistors become cutoff, saturated, or breakdown in one or more gain stages of the amplifier. Typically, the CMR permits the common mode voltage (V
CM
) to approach within a few volts of either power supply voltage before the amplifier performance is degraded.
A typical differential amplifier (
100
) is shown in FIG.
8
. As shown in the figure, a current source I
DIFF
sources a current into node
1002
. Transistor M
1
has a source connected to node
1002
, a gate connected to IN
N
and a drain connected to node
1001
. Transistor M
2
has a source connected to node
1002
, a gate connected to IN
P
, and a drain connected to node
1003
. Transistor M
3
is a diode-connected transistor with a gate and drain connected to node
1001
, and a source connected to V
SS
. Transistor M
4
has a gate connected to node
1001
, a drain connected to node
1003
, and a source connected to V
SS
. Transistor M
5
has a gate connected to node
1003
, a drain connected to V
OUT
and a source connected to V
SS
. A second current source I
OUT
sources a current into the drain of transistor M
5
(V
OUT
). A capacitor (C
C
) is connected between V
OUT
and node
103
.
Transistors M
1
and M
2
are a matched pair of PMOS transistors that form a differential input stage of the differential amplifier (
1000
). Transistors M
3
and M
4
form an NMOS current mirror, acting as a load for the differential input pair (M
1
, M
2
). Current source I
DIFF
supplies a “tail current” to bias the differential input pair transistors into their active region of operation. NMOS transistor M
5
serves as an amplifier, with an input at node
1003
and an output at V
OUT
. A capacitor (C
C
) reduces the gain of the amplifier at high frequencies to provide a stable amplifier by Miller compensation.
The input differential pair transistors (M
1
, M
2
) limit the CMR of differential amplifier
1000
. Transistors M
1
and M
2
must be biased in saturation for the amplifier to function properly. A typical threshold voltage of a PMOS transistor (V
TP
) is on the order of −1V. To remain in saturation, the source-to-gate voltage (V
SG
) of transistors M
1
and M
2
must be biased active (V
SG
≧|V
TP
|). Since the input differential pair transistors will be cutoff when V
CM
(the DC level at INM and INP) approaches the V
DD
power supply, the input differential pair transistors will operate as an amplifier when: V
G1
(max)=V
G2
(max)=V
CM
(max)≅V
DD
−|V
TP
|. The active load transistors (M
3
, M
4
), together with the input differential pair transistors (M
1
, M
2
) determine the minimum V
CM
for which the amplifier will operate properly. Transistors M
1
and M
2
must also have a source-to-drain voltage (V
SD
) that exceeds the saturation voltage (V
SD
≧V
SG
−|V
TP
|). The typical threshold voltage of a NMOS transistor (V
TN
) is on the order of +1V. The load transistors M
3
, M
4
must be biased active (V
GS3
=V
GS4
>V
TN
). The minimum V
CM
for amplifier
1000
, is determined by: V
G1
(min) =V
G2
(min)=V
CM
(min)≅V
SS
+V
TN
−|V
TP
|. Thus, amplifier
1000
does not operate as a rail-to-rail amplifier.
The unity-gain bandwidth (GBW) is defined as the frequency where the gain is 0 dB. Since C
C
creates a dominant pole in the amplifier, the unity gain bandwidth (GBW) is &ohgr;≅g
m
/C
C
, where g
m
is the trans-conductance of the amplifier.
SUMMARY OF THE INVENTION
In accordance with the invention, the above and other problems are solved by an apparatus and method that reduces an overall gain in a rail-to-rail amplifier. The reduced overall gain permits employment of a reduced size compensation network in compensating the apparatus, and thereby reduces the “on-chip” area used by the compensation network.
Briefly stated, the present invention relates to a rail-to-rail amplifier having a first and second input stage amplifier, and an output stage amplifier that provides rail-to-rail operation. The rail-to-rail amplifier is driven by an input signal with a particular common-mode voltage. The first amplifier is active during a first range of common-mode voltages, while the second amplifier is active during a second range. A monitor circuit includes an input differential pair that is sized to operate at the same common-mode voltages as the first input differential pair in the first amplifier. The monitor circuit senses when the first amplifier has reached a condition where the amplifier begins to stop working by monitoring a current flowing in the input differential pair. The monitor circuit controls the bias current in the second amplifier's bias circuit such that the second amplifier is enabled when the current in the input differential pair drops down towards zero. The outputs of the first input stage amplifier and the second input stage amplifier are coupled to the input of the output stage amplifier. Since the first and second input stage amplifiers are not on at the same time, the overall gain in the amplifier is reduced. Reducing the gain of the rail-to-rail amplifier results in a reduced size of a compensation capacitor that is coupled across the input and output of the output stage amplifier. The reduction in gain and compensation capacitor results in a lowered amount of chip space and reduced cost for the rail-to-rail amplifier.
According to a feature of the invention, an apparatus for amplifying a signal includes a first and second input stage amplifier, and an input amplifier monitor circuit. The input amplifier monitor circuit senses an operating state of at least one of the input stage amplifiers to produce a control signal. The control signal is used to control one of the input stage amplifiers such that the overall gain of the apparatus is limited.
In one embodiment of the invention, the first input stage amplifier operates over a first range of common-mode voltages. The gain is limited by disabling the second amplifier when the first input stage amplifier is operating.
In another embodiment of the invention, the apparatus further includes a controller circuit. The controller circuit disables the second amplifier in response to the control signal when the common-mode voltage is in a first range. The controller circuit enables the second amplifier in response to the control signal when the common-mode voltage is in a second range.
In a further embodiment of the invention, the apparatus further includes a controlled bias circuit that has a bias output. The bias output is coupled to the second input stage amplifier. The controlled bias circuit selectively disables the second input stage amplifier by disabling the bias output in response to the control signal.
In another embodiment of the invention, the first input stage amplifier has a first differential input pair of transistors. The input amplifier monitor circuit includes a second differential input pair of transistors. The transistors of the first differential input pair and the second differential input pair are of a same type (e.g. PMOS). When the second differential input pair is operating at a common-mode voltage in a first range, the second input stage amplifier is disabled by the control signal. Also, the first differential input pair and the second differential input pair may share a common source connection.
In yet
Choe Henry
Hertzberg Brett A.
National Semiconductor Corporation
Pascal Robert
LandOfFree
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