Radix 2 architecture and calibration technique for pipelined ana

Details Radix 2 architecture and calibration technique for pipelined ana Radix 2 architecture and calibration technique for pipelined ana

1994-11-10

1997-09-16

Williams, Howard L.

Coded data generation or conversion

Converter compensation

341161, H03M 138, H03M 106

Patent

active

056685491

ABSTRACT:
In a pipelined radix 2 analog to digital converter, a method of analog residue formation uses an overflow reduction stage which takes an analog input and outputs a digital value of +2, 0, or -2 and an analog residue which is twice the analog input minus the digital output value times a reference voltage. A calibration technique allows a pipelined analog to digital converter using the overflow reduction stages to produce a corrected output requiring one addition per pipeline stage. The residue portion of the overflow reduction stage can be constructed using an operational amplifier, two capacitors, one of which has twice the capacitance of the other, and three on-off type switches. A radix 2 pipelined converter is constructed using a combination of standard 1-bit stages and overflow reduction stages. The analog residue is passed from stage to stage as an amplifier remainder as the digital codes are extracted in a pipelined analog to digital converter. The overflow reduction stage reduces out-of-range residues back to in-range residues. Using three digital output values where the difference between any two is greater than one raw output code prevents the possibility of multiple representations of the same code and thus allows for the prevention of non-monotonic input-output transfer functions. The self-calibration and raw output code correction schemes prevent non-monotonicities and missing codes in the input-output transfer functions.

REFERENCES:
patent: 4760376 (1988-07-01), Kobayashi et al.
patent: 5027116 (1991-06-01), Armstrong et al.
patent: 5510789 (1996-04-01), Lee
Patent Abstracts of Japan vol. 60 No. 87 (e-108), 25 May 1982 &JP, A 80 097804 (Advantesst ) 6 Feb. 1982.
"A 10-b 20-Msample/s Analog-to-Digital Converter," by Stephen H. Lewis, H.Scott Fetterman, George F. Gross, Jr., R. Ramachandran, and T.R. Viswanathan, IEEE Journal of Solid-State Circuits, vol. 27, No. 3, Mar. 1992, pp. 351-358.
"A 12-b 600 ks/s Digitally Self-Calibrated Pipelined Algorithmic ADC," by Hae-Seung Lee, IEEE Journal of Solid-State Circuits, vol. 29, No. 4, Apr. 1994, pp. 509-515.
"A 15-b 1-Msample/s Digitally Self-Calibrated Pipeline ADC," by Andrew N. Karanicolas, Hae-Seung Lee, and Kantilal L. Bacrania, IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993, pp. 1207-1215.
"Clever Designs Spawn 40-MHz/10-Bit/0.2-W ADCS", by Frank Goodenough, Electronic Design, Jan. 24, 1994, pp. 123-128.

Affiliated with

Also associated with

Rating

Radix 2 architecture and calibration technique for pipelined ana does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Radix 2 architecture and calibration technique for pipelined ana, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Radix 2 architecture and calibration technique for pipelined ana will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-221596