Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
1998-02-12
2001-01-16
Vo, Don N. (Department: 2734)
Pulse or digital communications
Equalizers
Automatic
C375S235000, C375S326000, C375S350000, C375S355000
Reexamination Certificate
active
06175591
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a radio receiving apparatus and, more particularly, to a radio receiving apparatus having a clock regenerating circuit for regenerating a clock, which is synchronized to a symbol clock on the transmitting side, and identifying a demodulated signal by the timing of the regenerated clock.
A clock regenerating circuit used in the receiver section of a multiplexed radio apparatus is referred to also as a BTR (Bit Timing Recovery) circuit and is used to regenerate a clock component from a signal obtained by demodulating a multilevel quadrature modulated signal such as a signal modulated by PSK (Phase Shift Keying) or QAM (Quadrature Amplitude Modulation). The clock regenerated by the clock regenerating circuit is used as the operation timing signal of a device such as an AD converter for identifying a demodulated signal. To this end, it is required that the phase of the regenerated clock be made to coincide with the timing at which the level of the demodulated signal is identified (which timing is the moment at which the so-called eye pattern is open to the maximum extent). However, owing to changes in line conditions such as caused by a change in temperature, there are instances where the clock develops a phase shift. Accordingly, there is demand for a clock regenerating circuit that is capable of regenerating a highly precise signal discriminating clock by detecting such a phase shift in highly accurate fashion and compensating for the clock phase shift in an accurate matter.
FIG. 19
is a diagram showing the construction of the receiver section of a multiplexed radio apparatus according to the prior art. The receiver section has a clock regenerating circuit for identifying a demodulated signal in highly precise fashion.
(a) Overall Configuration
An intermediate-frequency signal IF-IN is obtained by applying frequency modulation to a received signal. The received signal has been subjected to multilevel quadrature modulation such as PSK or QAM (e.g., 16 QAM).
A quadrature detector
22
orthogonally detects the intermediate-frequency signal IF-IN and outputs two types of baseband signals (an I-channel signal Ich and a Q-channel signal Qch), which are 90° out of phase (i.e., in quadrature). AD converters
23
,
24
respectively convert the I- and Q-channel signals Ich, Qch, which are output by the quadrature detector
22
, to digital data. A transversal equalizer
25
applies equalization processing to the digital data output by the AD converters
23
,
24
. A clock phase signal generator
26
detects the phase components of a regenerated clock and outputs a clock phase signal. A clock regenerating circuit
27
regenerates a clock signal CLK synchronized to symbol clock that is included in the demodulated signal.
(b) Quadrature Detector
The quadrature detector
22
includes an intermediate-frequency amplifier
22
a
, a hybrid circuit (H)
22
b
for branching the intermediate-frequency signal, a local oscillator
22
c
, which oscillates at a carrier frequency fc, a hybrid circuit
22
d
for separating the output signal of the local oscillator
22
c
into two signals that are 90° out of phase, mixer circuits
22
e
,
22
f
for orthogonally detecting the intermediate-frequency signal by mixing it with two orthogonal signals and outputting baseband in-phase and quadrature signals Ich, Qch, respectively, and roll-off filters
22
g
,
22
h
for imparting a roll-off characteristic to the baseband in-phase and quadrature signals Ich, Qch.
(c) Transversal Equalizer
The transversal equalizer
25
has the construction of a well-known two-dimensional transversal equalizer of the kind shown in FIG.
20
. The transversal equalizer includes transversal filters
25
a
-
1
,
25
a
-
2
for eliminating transmission path distortion of the I-channel signal, transversal filters
25
b
-
1
,
25
ba
-
2
for eliminating transmission path distortion of the Q-channel signal, and subtractors
25
c
,
25
d
. The subtractor
25
c
subtracts the Q-channel signal from the I-channel signal to cancel the quadrature component (Q-channel component) contained in the I-channel signal. The subtractor
25
d
subtracts the I-channel signal from the Q-channel signal to cancel the quadrature component (I-channel component) contained in the Q-channel signal.
As will be described later, each of the transversal filters
25
a
-
1
-
25
b
-
2
is constituted by N-tap FIR filters in which the coefficients can be changed. The coefficients are decided so as to compensate for transmission path distortion. If the I- and Q-channel signals are each expressed by eight bits in 16 QAM, the two high-order bits represent data and the six low-order bits represent the error due to waveform distortion, etc. In case of data that is positive, the relationship between identification threshold values of two high-order bits and digital data is as illustrated in FIG.
21
. (1) When a third bit E is “1”, the digital data is greater than an intermediate value (the dashed line) of the identification threshold values. (2) When E is “0”, the digital data is less than the intermediate value. In order to eliminate the effects of transmission path distortion, it will suffice to perform control in such a manner that the value of the six low-order bits will approach the intermediate value (the ideal value) of the identification threshold values.
Accordingly, in a case where data is positive, control is performed in such a manner that the output data of the transversal filter becomes small if E=“1” holds and large if E=“0” holds. In a case where data is negative, control is performed in such a manner that the output data of the transversal filter becomes large if E=“1” holds and small if E=“0” holds. The transversal filters
25
a
-
1
25
b
-
2
eliminate the influence of transmission path distortion by causing the coefficients of the FIR digital filters to converge toward predetermined values in accordance with the above-described logic.
An example of such a transversal filter is a five-tap transversal filter
250
shown in FIG.
22
. The transversal filter
250
includes four delay circuits
251
1
-
251
4
for successively delaying input data by one sampling time period (one symbol clock) at a time, coefficient decision/multiplier units
252
0
-
252
4
for automatically deciding coefficients C
2
-C
−2
based upon the polarity of the input data and of data D output by each of the delay circuits and an error signal E (“1”, “0” of a third bit), and for multiplying the input data and the output data of the delay circuits by the coefficients C
2
-C
−2
, and adders
253
1
-
253
4
for summing the products from the coefficient decision/multiplier units
252
0
-
252
4
.
FIG. 23
is a diagram illustrating the details of part of the transversal filter
250
. Here the decision/multiplier units
252
0
,
252
1
are shown in detail. The decision/multiplier units
252
0
,
252
1
include exclusive-OR (EOR) circuits EOR
1
, EOR
2
, respectively, for obtaining the exclusive-OR between (a) the polarity of the input data and the polarity (the most significant bit MSB) D of the data output by the respective delay circuits and (b) the error signal E of the transversal filter, up/down counters UDC
0
, UDC
1
, respectively, for incrementing or decrementing the coefficients C
2
, C
1
in dependence upon the output of the EOR circuit, and multipliers MLP
0
, MLP
1
, respectively, for multiplying the input data and delay circuit output data by the coefficients C
2
, C
1
, respectively.
The coefficient C
2
becomes one larger if the exclusive-OR of the polarity D of the input data and the error signal E is “1” and one smaller if the exclusive-OR is “0”. The coefficient C
1
becomes one larger if the exclusive-OR of the output data polarity D of the delay circuit
251
1
and the error signal E is “1” and one smaller if the exclusive-OR is “0”. By virtue of this operation, the coefficient values are controlled in such a manner that the value (error) E of the third bit onward of the digital data o
Fujitsu Limited
Helfgott & Karas P.C.
Vo Don N.
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