Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2002-12-23
2004-06-29
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S723000, C257S777000
Reexamination Certificate
active
06756681
ABSTRACT:
TECHNICAL FIELD
These teachings relate generally to integrated circuits (ICs) and, more specifically, relate to radio frequency (RF) ICs and to techniques for stacking ICs in three dimensional (3D) packaging arrangements.
BACKGROUND
In order to reduce the size of devices certain IC stacking structures have been developed. The stacking structures rely on a through-hole interconnection structure, also referred to in the art as a feedthrough or as a via, for making vertical connections between ICs that are stacked one upon another. In combination with the horizontal connections made within the ICs themselves, this technique provides a 3D IC packaging structure, thereby increasing the density and reducing the required package area. As compared with conventional wire-bond interconnections, the 3D packaging structure has a much greater potential for miniaturization.
A problem exists, however, when one of the ICs to be stacked is an IC that handles RF signals, such as those of about one GHz (10
9
Hertz) and greater, as the electrical performance is degraded due at least in part to insertion losses experienced by the RF signals at the through-hole interconnection structures. This problem relates to the fact that, in conventional 3D IC packaging approaches, the IC substrates (Si) typically have a resistivity of about 10 ohms-centimeter (10 ohms-cm) in order to enable the substrate to function as a ground. A result of the use of such low resistivity substrate material is that the substrate can appear as a capacitor to a high frequency signal, and can thereby deteriorate the signal.
At present, the application of through-hole interconnections in 3D IC structures is assumed for low-speed digital, or low frequency applications such as memory modules. Reference may be had to K. Kondo et al., “High Aspect Ratio Copper Via Fill used for Three Dimensional Chip Stacking”, 2002 ICEP Proceedings, pp. 327, for a description of current state-of-the-art through-hole technology in the context of 3D IC stacking.
General reference with regard to a wafer stacking technique that can involve an RF circuit may be made to U.S. Pat. No. 6,489,217B1, Method of Forming an Integrated Circuit on a Low Loss Substrate, A. Kalnitsky et al., Dec. 3, 2002 (Maxim Integrated Products, Inc.), such as FIG.
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and col. 4, lines 43-53. This patent discloses in part varying the dopant concentration of a silicon substrate or an epitaxial layer in order to increase the resistivity thereof to several thousand ohms-cm (col. 3, line 62 to col. 4, line 6).
SUMMARY OF THE PREFERRED EMBODIMENTS
The foregoing and other problems are overcome, and other advantages are realized, in accordance with the presently preferred embodiments of these teachings.
This invention provides for the use of the through-hole interconnection structure for not only low-speed and low frequency ICs, but also for RF and other high-speed application ICs. By the use of this invention an RF IC, or other type of high-speed IC, can be stacked with other types of ICs to thereby benefit from the advantages inherent in miniaturized devices, such as SiP (System in Package) solutions.
This invention provides a method for forming a three dimensional integrated circuit stacked structure, as well as a stacked structure formed in accordance with the method. The method includes placing a first integrated circuit atop a second integrated circuit, and electrically connecting the first and the second integrated circuits at connection points. At least some of the connection points correspond to electrically conductive through-hole structures made through a silicon substrate of the first integrated circuit. The first one of the integrated circuits contains circuitry operating at frequencies equal to or greater than about 1 GHz, and the silicon substrate has a resistivity of at least about 100 ohms-cm. The result is that the electrical performance is not degraded, as the RF signal insertion loss at the through-hole interconnection structures is significantly reduced.
In an exemplary embodiment the first integrated circuit contains RF circuitry and the second integrated circuit contains baseband circuitry. The second integrated circuit has a second silicon substrate that may also have a resistivity of at least about 100 ohms-cm. In the preferred embodiment the first and the second integrated circuits form a part of a wireless communications device, such as a cellular telephone.
REFERENCES:
patent: 5063177 (1991-11-01), Geller et al.
patent: 5882997 (1999-03-01), Sur et al.
patent: 6185107 (2001-02-01), Wen
patent: 6478883 (2002-11-01), Tamatsuka et al.
patent: 6489217 (2002-12-01), Kalnitsky et al.
patent: 2003/0119308 (2003-06-01), Geefay et al.
Harrington & Smith ,LLP
Wilson Allan R.
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