Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Nonlinear amplifying circuit
Reexamination Certificate
2001-05-10
2003-03-25
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Nonlinear amplifying circuit
C330S261000
Reexamination Certificate
active
06538501
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a radio frequency amplifier. Such an amplifier may be used in a tuner, for example as an input stage or as part of a mixer of a superheterodyne tuner. The present invention also relates to a tuner including such an amplifier.
2. Description of the Prior Art
In radio frequency tuners, it is desirable to have an input stage which provides good input impedance matching from DC to several GHz while keeping the noise figure to a minimum. It is common for tuners to be implemented partially or wholly as integrated circuits and the power dissipation must be maintained sufficiently low in order for such integrated circuits to be formed in relatively cheap packages so as to make such devices economically viable. The requirement to maintain relatively low power dissipation generally conflicts with the requirements of good signal handling and low noise figure.
In order to provide a well-defined input impedance, a series shunt feedback arrangement of the type illustrated in
FIG. 1
of the accompanying drawing has been widely used. In particular, this type of radio frequency amplifier or input stage of a tuner comprises an amplifier
1
having a gain of −A and a shunt feedback resistor
2
having a value Rf. The input impedance Rin of the stage is then given by the expression:
Rin=Rf
/(1
+A
)
so that the input impedance can effectively be selected, within limits, by the choice of the value Rf of the resistor
2
.
An arrangement of this type is illustrated in more detail in
FIG. 2
of the accompanying drawings. The input of the stage is connected to the input of a transconductance stage
3
having a transconductance −gm. The output of the transconductance stage
3
is supplied to a buffer
4
having a gain of unity. The output of the stage
3
is also provided with a load impedance illustrated as a resistor
5
connected to ground gnd. The signal at the input is thus amplified and inverted in phase by the transconductance stage
3
and the output voltage of the stage
3
is developed across the load
5
. This is buffered by the buffer
4
before being supplied to the output of the stage and to the feedback resistor
2
. The amplifier
1
of
FIG. 1
is thus implemented as the transconductance stage
3
, the load impedance
5
and the buffer
4
and the gain A is given by the product of the transconductance of the stage
3
and the value of the load
5
.
FIG. 3
of the accompanying drawings illustrates a discrete circuit implementation of the amplifier illustrated in FIG.
2
. The transconductance stage
3
comprises an npn transistor
6
connected in the common-emitter configuration with the collector being connected via the load resistor
5
to a supply line vcc. The emitter of the transistor
6
is connected via an emitter degeneration resistor
7
to ground gnd.
The buffer
4
comprises a transistor
8
connected as an emitter follower with its collector connected to the supply line vcc and its emitter connected to the output of the stage and via a constant current source
9
to ground gnd. The base of the transistor
8
is connected to the collector of the transistor
6
and the emitter of the transistor
8
is connected via the feedback resistor
2
to the base of the transistor
6
. The transconductance of the stage
3
is given by 1/(Re+re), where Re is the value of the emitter resistor
7
and re is the diode impedance of the transistor
6
.
The arrangement shown in
FIG. 3
may be used as a low noise amplifier (LNA) as an input stage of a tuner for receiving radio frequency signals, for example from an aerial or cable distribution system.
The LNA shown in
FIG. 3
may form part of a mixer and an arrangement of this type is illustrated in
FIG. 4
of the accompanying drawings. In this arrangement, the output of the LNA is connected to another common-emitter transconductance stage comprising a transistor
10
provided with an emitter degeneration resistor
11
. The collector of the transistor
10
is connected to a single-balanced Gilbert mixer comprising differential transistors
12
and
13
and a load resistor
14
. The bases of the transistors
12
and
13
receive differential local oscillator signals Lo− and Lo+ and the intermediate frequency output is formed across the load resistor
14
.
An alternative mixer arrangement is illustrated in
FIG. 5
of the accompanying drawings. In this arrangement, the transconductance stage comprising the transistor
10
and the resistor
11
of
FIG. 4
is omitted. Instead of connecting the collector resistor
5
to the supply line vcc, it is connected directly to the Gilbert mixer. Such an arrangement reduces the number of components of the mixer and provides a power-efficient arrangement. However, the maximum conversion gain is limited.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, there is provided a radio frequency amplifier comprising: a first transconductance stage whose input forms the input of the amplifier and whose output forms the output of the amplifier and is connected to a first load impedance; and a second transconductance stage whose input is connected to the output of the first stage and whose output is connected to the input of the first stage and to a second load impedance, the product of the transconductances of the first and second stages being negative.
The first stage may comprise at least one transistor of a first conductivity type and the second stage may comprise at least one transistor of a second conductivity type opposite the first type. The transistors may be bipolar transistors or field effect transistors, such as metal oxide silicon field effect transistors.
The first stage may comprise a differential pair of first and second transistors. The emitters of the first and second transistors may be connected to a first constant current source via respective first emitter resistors. The collectors of the first and second transistors may be connected to the amplifier output via respective first collector resistors whose values are substantially equal to the values of the first emitter resistor.
The second stage may comprise a second differential pair of third and fourth transistors. The emitters of the third and fourth transistors may be connected to a second constant current source via respective second emitter resistors. The collectors of the third and fourth transistors may be connected to respective second collector resistors constituting the second load impedance.
The collectors of the first and second transistors may be connected to the bases of the third and fourth transistors, respectively, and the collectors of the third and fourth transistors may be connected to the bases of the second and first transistors, respectively.
The collectors of the first and second transistors may be connected to the emitters of third and fourth differential pairs of transistors, respectively, of the first conductivity type. The third differential pair may comprise fifth and sixth transistors and the fourth differential pair may comprises seventh and eighth transistors whose bases are connected to the bases of the fifth and sixth transistors, respectively, and whose collectors are connected to the collectors of the sixth and fifth transistors, respectively.
According to a second aspect of the invention, there is provided a tuner including an amplifier according to the first aspect of the invention.
It is thus possible to provide an amplifier having an improved noise figure. This may be achieved while maintaining a relatively low power dissipation and a well-defined input impedance. The amplifier may be formed in a relatively low cost integrated circuit package.
REFERENCES:
patent: 4300102 (1981-11-01), Inoue
patent: 5541538 (1996-07-01), Bacrania et al.
patent: 5952880 (1999-09-01), Voorman et al.
patent: 2 295 934 (1996-06-01), None
Thompson Hine LLP
Wells Kenneth B.
Zarlink Semiconductor Limited
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