Radiation tolerant flash FPGA

Details Radiation tolerant flash FPGA Radiation tolerant flash FPGA

2000-12-14

2001-11-27

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290

Reexamination Certificate

active

06324102

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to field programmable gate array (FPGA) devices. More particularly, the present invention relates to FPGA integrated circuits employing flash memory as the programming medium and to providing radiation resistant flash FPGA integrated circuits.
2. The Prior Art
FPGA integrated circuits are well known in the art. The programming mechanisms for FPGA devices include antifuses, static random access memory (SRAM) devices and flash memory. Flash memory based FPGA integrated circuits usually comprise one or more floating gate flash MOS transistors. The one or more floating gate flash MOS transistors are used to drive the gate of a transistor programming switch that selectively interconnects desired circuit nodes.
When these prior-art flash-based FPGA devices are subjected to radiation, the charge stored on the floating gates of the flash transistors slowly leaks off, thus gradually degrading the drive signal provided to the transistor switch that is used to make the desired interconnection. The effect of radiation exposure on the floating gate flash transistors is cumulative. After a sufficient exposure to radiation, enough charge has leaked from the floating gates of the flash transistors so that the state of the switching transistor cannot be guaranteed.
BRIEF DESCRIPTION OF THE INVENTION
A radiation tolerant flash memory cell switch for FPGA and other applications according to the present invention includes a programming transistor switch coupled between two circuit nodes to be selectively connected to one another. A floating gate flash memory switch control circuit has a switch-control node coupled to the gate of the programming transistor switch. A sense transistor has a source coupled to the switch-control node, a gate coupled to a word line and a source coupled to a bit line. An addressing circuit is coupled to the word line and the bit line to periodically address the sense transistor. First and second sense amplifiers are coupled to the bit line. The first sense amplifier has a first current trip point higher than the current trip point of the second sense. Charge-leakage sensing logic is coupled to the first and second sense amplifiers and configured to generate a charge-leakage threshold signal when the sense transistor is addressed and the second sense amplifier has tripped but the first sense amplifier has not tripped. FPGA programming circuitry is coupled to the floating gate flash memory switch control circuit to reprogram the FPGA in response to the charge-leakage threshold signal.
In an illustrative embodiment contemplated herein, the floating gate flash memory switch control circuit includes a first floating gate flash transistor having a source coupled to a first potential, a drain, and a gate and a second floating gate flash transistor having a source connected to the drain of the first floating gate flash transistor to form the switch-control node, a gate coupled to the gate of the first floating gate flash transistor, and a drain coupled to a second potential. The switch node is coupled to the gate of the transistor programming switch.
A method according to the present invention for providing radiation tolerance to a flash-based FPGA integrated circuit employing a programming transistor switch coupled between two circuit nodes to be selectively connected to one another, the programming transistor switch having a gate and a floating gate flash memory switch control circuit having a switch-control node coupled to the gate of the programming transistor switch comprises periodically sensing a drive signal on the switch-control node during normal operation of the FPGA integrated circuit to determine if the drive signal is at a level below a refresh threshold. If the drive signal is at a level below the refresh threshold the FPGA integrated circuit is reprogrammed.


REFERENCES:
patent: 5940323 (1999-08-01), Kwon

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