Radiation hardened timer

Details Radiation hardened timer Radiation hardened timer

2001-09-04

2003-04-08

Lam, Tuan T. (Department: 2816)

Oscillators

Plural oscillators

Selectively connected to common output or oscillator...

C331S074000

Reexamination Certificate

active

06545551

ABSTRACT:

BACKGROUND OF THE INVENTION
Currently available high-stability timing references can be hardened to survive a high radiation dose rate environment, but cannot operate in such an environment. Timing references hardened to operate under high radiation dose rate are inherently less stable than needed for some high radiation applications.
The extremely high dose rate events of interest are of nanosecond to microsecond duration and the photocurrents they induce decay to negligible levels within milliseconds. It is therefore sufficient to shut down the highly stable reference for periods of a few milliseconds to a few hundred milliseconds. Timing references hardened to continue operation through such radiation events are sufficiently stable over such short periods. So the disclosed radiation-hardened timer, also referred to as RHT, employs a highly stable non-operate-through oscillator, a less stable operate-through oscillator, and a digital interface circuit between the two: The function of the interface circuit is to calibrate the less stable oscillator to the more stable one, and to select which of the two is used as the timing reference.
The two timing references are independent asynchronous oscillators operating at different frequencies. The highly stable oscillator frequency, f
1
, is chosen to suit the needs of the system for which the RHT will serve as a time base. The radiation hardened oscillator frequency, f
2
, is chosen to be slightly more than an integer multiple of f
1
. Since the integer selected is the approximate ratio of the two frequencies, it shall subsequently be referred to as R. The RHT performance is improved by selecting R as large as possible, but the design is simplified if it is a power of two. For the prototype upon which this patent is based, R is four. The exact value of f
2
is chosen such that the maximum expected drift of f
2
will not allow it to drop below R*f
1
.
If f
2
/f
2
were exactly R, then f
2
would only need to be divided by R to be used as the timing reference. Since f
1
/f
2
is actually slightly larger than R, the occasional divide by (R+1) is needed to correct for accumulated error. The calibration algorithm determines how often a divide by (R+1) is needed; the generation algorithm determines when the divisions by (R+1) are preformed. Together these two halves of the interface algorithm are called the Delta-Mirror Algorithm (DMA).
If f
2
/f
1
were slightly less than R, then correcting for accumulated error would require the occasional divide by (R−1). This would result in an occasional clock cycle that was significantly shorter than expected. Such a short cycle could cause a setup time violation in a digital circuit, so f
2
is selected such that f
2
/f
1
will never drop below R.
While in a benign environment, the highly stable oscillator signal is passed straight through as the RHT output. This signal also drives the output counter, a counter containing enough bits to count high enough to obtain the required system accuracy. For 1 PPM accuracy, as in the prototype, the output counter needs to be able to count to one million divided by R. This results in a million counts of the radiation hardened oscillator between successive roll-overs of this counter. An 18 bit counter can count up to 262144, so the prototype uses an 18 bit counter. Successive roll-overs of the output counter then define a time interval referred to as the “calibration interval” and the “correction interval”. During this interval, the radiation hardened oscillator puts out slightly more than R*2
18
cycles, or just over one million. Division of the correction interval into more than a million segments, results in a timing accuracy of better than 1 PPM.
When the output counter rolls over, another counter, the backup counter, is reset to zero. The backup counter then counts pulses from the backup oscillator (f
2
). The count of f
2
will reach 262144 R times and then count up to a small number by the next roll over of the output counter. This “small” number, called Delta, is the number of times the backup oscillator output would need to be divided by (R+1) to produce an output frequency of f
1
. The backup register must contain enough bits to count to the largest possible value of Delta. For simplicity, the prototype uses an 18 bit register as the backup counter.
At output counter roll over, Delta is copied into another register, called the correction mask register, but with the bit order reversed. The least significant bit of Delta becomes the most significant bit of the correction mask, the second least significant becomes the second most significant, and so on. This reversal of the bit order is called the “mirror” function. Should a radiation event require circumvention of the reference oscillator before the next roll over of the output register, the mirror of Delta currently stored in the correction mask will be used to generate the output from the backup oscillator.
Since the prototype calibration interval is 262144 counts of the reference oscillator and the prototype reference oscillator is 11.7504 MHz, the RHT recalibrates itself approximately once every 22.3 mS.
SUMMARY OF THE INVENTION
The RHT consists of a radiation hardened backup oscillator (f
2
) and an application specific integrated circuit (ASIC). There are with inputs to the ASIC from a reference oscillator, (the reference oscillator not being part of the RHT), from the backup oscillator, and from various controls.
The backup oscillator consists of a resonator employing only passive parts, and an amplifier which is actually an inverter gate and two input/output (I/O) drivers on the ASIC. The passive parts include a quartz crystal, resistors, capacitors, and inductors.
The ASIC is a Silicon On Insulator (SOI) process integrated circuit, specifically designed to enhance radiation hardness. Included in the ASIC are six counter/registers: the reference counter, the backup counter, the last state counter, the correction mask, the output counter, and the reference detector.
The size of the reference counter determines the accuracy of the RHT. The prototype employs an 18 bit counter, which when combined with an approximate frequency ratio, f
2
/f
1
, of 4 produces an accuracy of approximately 1 PPM.
The output counter, last state counter, and the correction mask must be the same size as the reference counter. The backup counter must be large enough to hold the largest likely value of delta and no larger than the reference counter. The prototype uses 18 bit registers for all five counters.
The logic connecting these registers is a synthsizable very-high-density-logic (VHDL) listing, implemented in both a Xilinx field-programmable-gate-array (FPGA) and in a Honeywell HX2000 Silicon-On-lnsulator (SOI) process ASIC.
The radiation hardened timer comprises an input from a reference oscillator of frequency f
1
; a backup oscillator of frequency f
2
, where f
1
and f
2
are asynchronous, and the nominal value of f
2
is slightly more than R times f
1
, where R is an integer; an N bit wide digital register serving as an output counter; an N bit wide digital register serving as a last state counter; an N bit wide digital register serving as a correction mask; a count, called Delta, representing the difference between f
2
and R times f
1
according to the formula f
2
≡(R+Delta/2
N
)*f
1
, the approximation due only to the fact that R, Delta, and N are all integers; a digital register wide enough to hold the largest expected value of Delta, but no more than N bits wide, employed to count the backup oscillator output; a digital divider which nominally divides the backup oscillator signal by R, but which divides it by R+1 when the requirements of a Delta-Mirror algorithm are met; a detector circuit that senses the presence or absence of the reference oscillator signal at the reference oscillator input; and an adjudicator circuit that passes either the reference oscillator signal through as the output if it is available, or the divided down backup oscillator signal if the ref

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