Fishing – trapping – and vermin destroying
Patent
1989-10-03
1991-06-04
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 34, 437 62, 437 63, 437 67, 437938, H01L 21265, H01L 2952, H01L 2978
Patent
active
050213598
ABSTRACT:
Integrated circuits with vertical isolated trenches are radiation hardened by providing vertical gate segments, preferably, of doped polycrystalline silicon, in the trenches and connected at the bottom of the trenches to a region of the same conductivity type. The surface devices may be complementary and the vertical gates may also be complementarily doped. A method of fabrication is described for a single crystal wafer, as well as SOI.
REFERENCES:
patent: 4786960 (1988-11-01), Jeuch
"Characterization of the Lateral and Vertical Parasitic Transistors in a Trench Isolated CMOS Process", M. C. Roberts, D. J. Foster, pp. 411-412.
"MOSFET Achieved by a Combination of Polysilicon Sidewall and SIMOX Technology", T. Ohno et al., Electronic Letters, pp. 559-560, May 86.
Rivoli Anthony L.
Wiles, Jr. William W.
Young William R.
Chaudhuri Olik
Griffis Andrew
Harris Corporation
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