Radiation hardened CMOS structure using an implanted P guard str

Details Radiation hardened CMOS structure using an implanted P guard str Radiation hardened CMOS structure using an implanted P guard str

1992-07-10

1993-06-15

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257547, 257648, 257921, 437 40, 437 63, 437 70, 437 50, 437196, H01L 2712, H01L 21265

Patent

active

052201929

ABSTRACT:
A radiation hardened NMOS transistor structure suited for application to radiation hardened CMOS devices, and the method for manufacturing it is disclosed. The new transistor structure is characterized by "P" doped guard bands running along and immediately underlying the two bird's beak regions perpendicular to the gate. The transistor and the CMOS structure incorporating it exhibit speed and size comparable to those of conventional non-rad-hard CMOS structure, relatively simple manufacturing, and excellent total-dose radiation hardness.

REFERENCES:
patent: 4498227 (1985-02-01), Howell et al.

Affiliated with

Also associated with

Rating

Radiation hardened CMOS structure using an implanted P guard str does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Radiation hardened CMOS structure using an implanted P guard str, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Radiation hardened CMOS structure using an implanted P guard str will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1045448