Radiation hardened CMOS master latch with redundant clock...

Details Radiation hardened CMOS master latch with redundant clock... Radiation hardened CMOS master latch with redundant clock...

2008-05-29

2010-06-08

Nguyen, Hai L (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S202000, C327S211000

Reexamination Certificate

active

07733144

ABSTRACT:
A radiation hardened master latch for use in a programmable phase frequency divider operating at GHz frequencies is implemented in deep submicron CMOS technology, and consists of two identical half circuits interconnected in a DICE-type configuration that makes the master latch immune to a single event upset (SEU) affecting at most one of its four data inputs. Each half circuit includes a clock input circuit with four sub-clock nodes each coupled by an inverter to a common clock input. The clock input circuit is configured to be redundant, such that the operation of the master latch half circuit is also immune to an SEU affecting at most one the inverters associated with the plurality of sub-clock nodes. The radiation hardened master latch resides in a design structure embodied in a machine readable medium storing information for designing, manufacturing and/or testing the master latch.

REFERENCES:
patent: 6326809 (2001-12-01), Gambles et al.
patent: 6327176 (2001-12-01), Li et al.
patent: 6696873 (2004-02-01), Hazucha et al.
patent: 7212056 (2007-05-01), Belov
patent: 7362154 (2008-04-01), Mo
patent: 7576583 (2009-08-01), Kuboyama et al.

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