Radially distributed transverse filter

Details Radially distributed transverse filter Radially distributed transverse filter

1998-07-29

2001-04-17

Ngo, Ohuong Dinh (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06219683

ABSTRACT:

BACKGROUND OF THE INVENTION
Transverse filters are multiple-stage spatial processing networks which allow for variable control of phase and/or amplitude response. Each stage, or tap, of a transverse filter includes a delay line and a leg. The delay lines of adjacent taps are coupled in series at a node. A signal applied to a tap is delayed a predetermined time interval by the delay line. The time interval is determined by the properties of the delay line material, i.e. the propagation constant, and by the geometry of the line layout, i.e. length and width. This is referred to as the “electric length” of the line. The delayed signal at each leg is applied to a multiplier. The attenuated signals of all taps are, in turn, summed at an adder. Phase/frequency equalizers are commonly applied to each delay line to avoid accumulation of phase/frequency and amplitude/frequency distortions of the delay lines at successive taps.
Variation in the electric length of taps in a filter, for example variation in the electric length of a delay line and/or the electric length of a leg can limit device performance. Assuming a trace delay of approximately 1.5 nsec per foot of trace, a difference in length between taps of as little as 1 inch can cause signals from different taps arriving at the adder to lag or lead each other by as much as 125 psec. In high-frequency applications, for example for the processing of signals of a frequency range on the order of 0.5 GHz, delay variations of such a high magnitude can have an adverse effect on filter response.
Variations in trace length of the leg between the node and the adder may be compensated for by selecting different delay line lengths for each tap. However, such a configuration would require different amounts of phase/frequency equalization at each tap and would complicate filter layout.
SUMMARY OF THE INVENTION
The present invention is directed to a transverse filter configuration which overcomes the limitations of conventional systems. Specifically, the taps of the transverse filter of the present invention are of substantially equal electric length. In this manner, imprecision due to propagation delay is mitigated and/or eliminated, and accurate processing of high-frequency signals can be achieved.
In a preferred embodiment, the transverse filter of the present invention comprises a plurality of delay lines of substantially equal propagation delay. The delay lines are sequentially connected at a plurality of nodes. The nodes are distributed substantially equidistant from a common position. An adder is located substantially at the common position. A plurality of attenuators are distributed radially about the common position and coupled between the nodes and the adder, such that the propagation delays of the attenuators are substantially equal.
In a preferred embodiment, the delay lines are of substantially equal electrical length. The attenuators are likewise of substantially equal electrical length. Each delay line and attenuator pair forms a tap, and all taps are preferably of equal electrical length. One of the taps is preferably an input tap for introducing an input signal to the filter. An input signal, applied to the input tap, is delayed as it propagates through the delay lines between nodes. The delayed signal at each node is attenuated by one of the attenuators, and the attenuated signals of all taps are summed at the adder to provide an output signal. The propagation delays of the respective signals through the taps are preferably substantially equal.
The nodes are preferably positioned substantially at vertices of a polygon. In a preferred embodiment, the polygon is an equilateral polygon, or circle.
Amplitude and/or phase correctors may be positioned along the delay lines, between nodes. The attenuators preferably comprise four-quadrant multipliers.


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