Racing circuit for controlling access of processor units to a co

Details Racing circuit for controlling access of processor units to a co Racing circuit for controlling access of processor units to a co

1978-04-12

1980-02-19

Chapnick, Melvin B.

Boots, shoes, and leggings

340147LP, G06F 918, H04Q 300, G06F 1300

Patent

active

041897668

ABSTRACT:
A racing circuit wherein request signals which are asynchronously and simultaneously generated by a plurality of processor units for requesting the use of a common resource such as a memory are temporarily stored, and one of the stored request signals is selected so that the corresponding processor unit may access and use the common resource. The circuit provides a buffer arrangement for causing a first received request signal to lock out other request signals which follow the first signal too closely, and for providing access to the common memory or other device in the order in which access requests were received. The processor unit may control the racing circuit so that the processor unit may attain the exclusive use of the common resource as long as it desires.

REFERENCES:
patent: 3445822 (1969-05-01), Driscoll
patent: 3492648 (1970-01-01), Olsen et al.
patent: 3543246 (1970-11-01), Adams, Jr.
patent: 3593302 (1971-07-01), Saito et al.
patent: 3603935 (1971-09-01), Moore
patent: 3919692 (1975-11-01), Kronies et al.
patent: 3934230 (1976-01-01), Salle et al.
patent: 4016539 (1977-04-01), Nanya
patent: 4121285 (1978-10-01), Chen
Christensen, "Programmable Priority Mechanism", in IBM Technical Disclosure Bulletin, vol. 17, No. 7, Dec. 1974, pp. 2052-2053.

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