Racefree CMOS clocked logic circuit

Details Racefree CMOS clocked logic circuit Racefree CMOS clocked logic circuit

1984-01-23

1986-09-23

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307481, 307279, 377 79, 377105, 377117, H03K 19096, H03K 2344, H03K 3037, G11C 1928

Patent

active

046137734

ABSTRACT:
A racefree CMOS clocked logic circuit includes a first CMOS clocked gate for selectively transferring an input signal according to a first clock pulse and providing an interstage signal corresponding to the input signal; and a second CMOS clocked gate, which is connected directly to the first CMOS clocked gate, for selectively transferring the interstage signal according to a second clock pulse and providing an output signal corresponding to the interstage signal. The operation of first CMOS clocked gate is synchronized to the first clock pulse, and the operation of second CMOS clocked gate is synchronized to the second clock pulse. The second clock pulse is in-phase with or identical to the first clock pulse so that signal races between the input signal and the output signal are eliminated.

REFERENCES:
patent: 3766408 (1973-10-01), Suzuki et al.
patent: 3887822 (1975-06-01), Suzuki
patent: 3925685 (1975-12-01), Suzuki
patent: 3937982 (1976-02-01), Nakajima
patent: 4040015 (1977-08-01), Fukuda
patent: 4063114 (1977-12-01), Morozumi
patent: 4114049 (1978-09-01), Suzuki
patent: 4164666 (1979-08-01), Hirasawa
patent: 4369379 (1983-01-01), Hull
Suzuki et al., "Clocked CMOS Calculator Circuitry," IEEE International Solid-State Circuits Conference, ISSCC, pp. 58-59, Wednesday, Feb. 14, 1973.
Goncalves et al., "A Racefree-Dynamic CMOS Technique for Pipelined Logic Structures," ESSCIRC Dig. Tech, Papers, pp. 141-144, 1982.

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