Race removal or reduction in latches and loops using phase skew

Details Race removal or reduction in latches and loops using phase skew Race removal or reduction in latches and loops using phase skew

2000-06-23

2001-10-30

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S219000

Reexamination Certificate

active

06310500

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention generally relates to logic circuits, and more particularly to a system and method for controlling the flow of data in loop circuits used, for example, in semiconductor memory devices.
BACKGROUND DESCRIPTION
Latches and other types of loop circuits are commonly used in digital design, and are especially prevalent in the flip-flop circuits of a semiconductor memory device. Improving operational efficiency of latches and loops, thus, has become a major concern of digital circuit designers.
FIGS.
1
(
a
)-(
c
) show three conventional latch circuits, each of which is phased by a logic voltage P, with P′ being the complement of P. In the latch of FIG.
1
(
a
), a phased inverter
2
is included along a forward path and a phased inverter
4
along a feedback path. In the latch of FIG.
1
(
b
), a plain (e.g., unphased) inverter
6
is connected to a switch
8
along a forward path and an inverter
10
is connected to a switch
12
along a feedback path. In the latch of FIG.
1
(
c
), two plain inverters
14
and
16
are connected in series to a switch
18
along a forward path, and a single switch
20
is included along a feedback path. Each of these latch circuits have input and output terminals, as shown, and the phased inverters are gated inverters. A well known implementation phased inverters
2
and
4
is shown in
FIG. 2
, and an implementation of the switches of FIGS.
1
(
b
) and
1
(
c
) is shown in FIG.
3
.
In operation, the latch circuits are enabled when P is at logic 1 and disabled when P is at logic 0. When enabled, signals from the input terminal and the output terminal race to set each other—the input tries to set the output via the forward path and (the preexisting value at the) output tries to set the input via the feedback path. The node that wins determines the resulting state of the latch. In order to ensure proper operation, the signal from the input terminal must always set the output. This means that the race in each latch has to be fixed so that the input terminal signal always wins.
A conventional method for fixing the race so that the input terminal signal always wins is shown in FIGS.
1
(
a
)-(
c
). Each feedback path is surrounded by a dashed box, which is labeled by a star (*). The star indicates that the path is weak or resistive compared to the forward path between the input and output terminals. The choice of a sufficiently large relative resistance ensures that the output always loses the race, resulting in the proper functioning of the latches.
The problems associated with using a resistive path in deciding a race conflict are as follows. A resistive path is typically implemented by increasing the length of a MOSFET's channel in comparison to its width. This increases the area of the transistor, with a concomitant increase in switching capacitance. Also, power consumption increases, both due to the increase in switching capacitance and due to the node setting races entertained (albeit in a fixed manner) by the solution. These two causes can also reduce the speed of operation of the circuit. Alternatives to increased switching capacitance can increase the number of transistors used in circuit implementation.
A need therefore exists for a method for resolving race conflicts in a loop circuit, such as a latch, in a more efficient manner compared with conventional methods.
SUMMARY OF THE INVENTION
It is a first object of the present invention to provide an improved method and apparatus for resolving race conflicts between input and output nodes of a loop circuit (e.g.,a latch), and especially one adapted for use in the flip-flop circuits of a digital memory.
It is a second object of the present invention to accomplish the first object by enabling/disabling a feedback path of the loop circuit using a phase waveform, and more specifically by skewing the phase of a signal that controls the flow of data along the feedback path relative to a signal that controls data flow along a forward path.
It is another object of the present invention to achieve the second object by delaying at least one of the rising and falling edges of a clock signal that drives the feedback path of the loop circuit, so that the feedback path outputs data to the forward path later in time than data supplied to the input node of the circuit, thereby ensuring that the data signal supplied to the input node always wins the race.
It is another object of the present invention to achieve the second object by delaying both the rising and falling edges of a clock signal which drives the feedback path of the looped circuit, so that the feedback path outputs data to the forward path later in time than data supplied to the input node of the circuit, thereby ensuring that the data signal supplied to the input node always wins the race.
It is another object of the present invention to provide a method and apparatus which resolves a race conflict between the input and output nodes of a looped circuit by using the combined approach of (1) skewing a phase signal for driving the feedback path and (2) making the feedback path weak or resistive.
It is another object of the present invention to apply the aforementioned method to unphased loop circuits once the loop circuits have been converted to a phased form.
These and other objectives of the invention are achieved by providing a method for controlling the flow of a signal in a loop circuit, wherein the loop circuit includes a signal line, an input node connected to the signal line, an output node, a forward path connected between the input node and output node, and a feedback path also connected between the input node and output node. In order to resolve race conflicts in the loop circuit, the method includes the step of generating a first control signal for controlling flow of a first data signal from the signal line to the output node along the forward path; inputting the first control signal into at least one circuit element along the forward path to cause the first data signal from the signal line to pass to the output node; generating a second control signal for controlling flow of a second data signal along the feedback path by generating skewing a phase of the second control signal relative to the first control signal so that said second data signal arrives at the input node after the first data signal supplied from said signal line; and inputting the second control signal into at least one circuit element along the feedback path.
The first and second control signals may be clock signals which drive the circuit elements along the forward and feedback paths, respectively. These clocks signals may be generated in accordance with one of two approaches. The first approach involves delaying a rising edge of the second control signal relative to the rising edge of the first control signal. The second approach involves delaying the rising and falling edges of the second control signal relative to the rising and falling edges of the first control signal. The rising and falling edges may be delayed by equal amounts. Further, race resolution may be introduced by making the feedback path resistive.
Through these approaches, the method of the present invention is able to achieve a number of advantages over conventional methods, including reduced power consumption, higher frequency response, reduced area, reduced design complexity, reduced number of transistors, reduced switching capacitance, and a reduced phase load in the form of, for example, a clock load.
In one embodiment of the loop circuit of the present invention, a circuit element along the feedback path is a phased (gated) inverter driven by the delayed clock signal and a circuit element along the forward path is a phased (gated) inverter driven by an undelayed clock signal.
In another embodiment, the forward and reverse paths each include an unphased inverter connected to a switch, with the switch in the forward path being driven by the undelayed clock signal and the switch in the feedback path being driven

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