Race condition improvements in dual match line architectures

Details Race condition improvements in dual match line architectures Race condition improvements in dual match line architectures

2007-04-10

2007-04-10

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S203000, C365S204000, C365S189070, C711S118000, C711S108000

Reexamination Certificate

active

11144123

ABSTRACT:
Dual match line circuits having race condition improvements. A dual match line circuit may include precharge logic configured to precharge each of a hit match line, a miss match line and an evaluate node to an asserted state, where a coupling device couples the hit and miss match lines to the evaluate node. The miss match line may discharge through a number of load devices that may be activated by respective miss signals. A positive feedback circuit coupled to the miss match line may accelerate its discharge. The hit match line may be additionally coupled to discharge through a discharge path. The hit and miss match lines may be electrically isolated from one another, such that when any of the respective miss signals is asserted, current from the hit match line does not discharge through the miss match line.

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Ho, et al., “A Process-Portable 64b Embedded Microprocessor with Graphics Extensions and a 3.6GB/S Interface,” International Solid-State Circuits Conference, ISSCC-2001, 3 pages.
Mohan, et al., “Low Power Dual Matchline Ternary Content Addressable Memory,” IEEE International Symposium on Circuits and Systems, (ISCAS), 2004, 4 pages.
U.S. Appl. No. 11/141,301, filed May 31, 2005.

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