Quotient digit selection logic for floating point division/squar

Details Quotient digit selection logic for floating point division/squar Quotient digit selection logic for floating point division/squar

1996-05-15

1999-09-21

Moise, Emmanuel L.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708497, 708499, 708500, 708504, G06F 738

Patent

active

059547898

ABSTRACT:
Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact, choosing a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a five bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fifth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit. Extra hardware is eliminated because it is no longer necessary to provide any extra mechanism for restoring the preliminary final partial remainder. Latency is improved because no additional cycle time is required to restore negative preliminary partial remainders. In an alternative embodiment, where the upper four bits of the estimated partial remainder are ones while the fifth most significant bit is zero, a quotient digit of negative one is chosen. This alternative embodiment allows correct exact results in all rounding modes including rounding toward plus or minus infinity.

REFERENCES:
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patent: 5272660 (1993-12-01), Rossbach
patent: 5357455 (1994-10-01), Sharangpani et al.
patent: 5386376 (1995-01-01), Girard et al.
Proceedings of the 12th Symposium of Computer Arithmetic, "167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages", J. Arjun Prabhu and Gregory B. Zyner, pp. 155-162, Jul. 19-21, 1995.
IRE Transactions on Electronic Computers, vol. EC-7, Sep., 1958, No. 3, "A New Class of Digital Division Methods*", James E. Robertson, pp. 218-222.
Proceedings 12th Symposium on Computer Arithmetic, "30-ns 55-b Shared Radix 2 Division and Square Root Using a Self-Timed Circuit", Gensoh Matsubara et al., pp. 98-105, Jul. 19-21, 1995.

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