Quiescent current testing of dynamic logic systems

Details Quiescent current testing of dynamic logic systems Quiescent current testing of dynamic logic systems

1995-09-25

1996-09-17

Canney, Vincent P.

Excavating

371 226, G06F 1100

Patent

active

055576206

ABSTRACT:
A system and method for quiescent current testing of dynamic logic circuitry. Nodes shorted to ground are detected during a dynamic pre-charge state. Nodes shorted to a power supply potential are detected by driving all nodes of interest to ground during a dynamic evaluation phase. Nodes of interest are driven to ground directly by one additional transistor per node or indirectly by logical propagation from upstream nodes. As a result, only two current measurements are needed for all shorted node faults, even for pipelined systems with multiple clocks. There is no need for input test signal sequences and no need for signal propagation to outputs for detection. Specific embodiments are provided for single-rail logic, single-rail pipelined systems, dual-rail logic and dual-rail pipelined systems. For single-rail pipelined systems, optional transistors between stages enable preservation of logical states during testing. For dual-rail logic, storage nodes and static nodes are forced to a logical state that is not possible during normal operation. For pipelined dual-rail logic, testing of alternate stages inherently preserves the logical state of the system during testing.

REFERENCES:
patent: 5057774 (1991-10-01), Verhelst et al.
patent: 5410551 (1995-04-01), Edwards et al.
EPO Search Report cited reference: Inspec Abstract No. B9408-1265B-039, C9408-5210-015 and IEEE Transactions On VLSI Systems, vol. 2, No. 2, pp. 241-248 (see abstract).
EPO Search Report cited reference: Inspec Abstract No. B9308-1265B-079 C9308-5210-035 and proceedings ATS 1992, pp. 64-69 (see abstract).

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