Queuing system

Details Queuing system Queuing system

2011-06-07

2011-06-07

Trost, IV, William (Department: 2472)

Multiplex communications

Data flow congestion prevention or control

Control of data admission to the network

C370S412000, C370S413000, C370S379000

Reexamination Certificate

active

07957275

ABSTRACT:
An improved architecture for switches and a method for transmitting data with the switching are disclosed. An increased amount of memory is utilized, operating at speeds lower than are required by Input Queued switches, and a simple scheduling algorithm. The architecture divides the input ports into groups, where each input port group has an associated set of memory elements. Incoming packets are routed to the appropriate element in the set of memory elements. The number of groups and the number of ports that are included in each group can be varied, allowing the architecture to be modified based on the system architecture, the semiconductor technology, and other design considerations.

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Chuang, et al., “Matching Output Queueing with a Combined Input Output Queued Switch,” Department of Electrical Engineering, Stanford Unviersity, 1999, 17 pages.

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