Queueing system for switches having fast circuit properties

Multiplex communications – Wide area network – Packet switching

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Details

370 62, 370 681, 379309, H04L 1216, H04M 342

Patent

active

054084687

ABSTRACT:
A digital switch serves a number of terminal units for switching signal traffic therebetween, the traffic being logically divided into data time slots and control time slots with control packets. It comprises a switch memory for receiving the data time slots, a control memory containing information for facilitating through connection of the data time slots in the switch memory, a control memory terminal for receiving the control time slots and control packets located therein, for writing information into the control memory, and for transmitting acknowledgement packets to called and calling ones of the terminal units, and an occupied/unoccupied memory cooperating with the control memory terminal and storing actual status of each of the terminal units. A queue system is associated with the control memory terminal and the occupied/unoccupied memory, the queue system including memory and control logic for effecting, in case a first terminal unit tries to establish connection to a second terminal unit that is occupied, queueing of a call request and transmission to the first terminal unit of an acknowledgement "request for connection queued" and, at the receipt of a request for disconnection from the second terminal unit, direct connection of the first terminal unit to the second terminal unit, and transmission of acknowledgements to the first and second terminal units with the information "connection effected" and "request effected", respectively.

REFERENCES:
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patent: 4953204 (1990-08-01), Cuschleg, Jr. et al.
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Patent Abstract of Japan, vol. 13, nr. 307, JP 1-082725 (Mar. 28, 1989).

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