Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2008-01-08
2008-01-08
Chan, Wing (Department: 2616)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S429000
Reexamination Certificate
active
10269414
ABSTRACT:
A parallel packet processing queueing architecture and method are described. A packet is divided up into cells. A first or start processor queue is selected for the first cell. The following cells of the packet are then placed in the queues in a predetermined order. An example of a predetermined order is placing the cells in consecutive processor queues modulo (the number of processor queues) after the start processor. Such a predetermined order is illustrated in the context of a per Cell Contiguous Queueing (CCQ) architecture. The architecture provides benefits of alleviating the pre-processing and post-processing buffering burdens and decreasing the amount of information required for reassembly of the packet.
REFERENCES:
patent: 5757771 (1998-05-01), Li et al.
patent: 5905725 (1999-05-01), Sindhu et al.
patent: 6072772 (2000-06-01), Charny et al.
patent: 6160819 (2000-12-01), Partridge et al.
patent: 6324165 (2001-11-01), Fan et al.
patent: 6424621 (2002-07-01), Ramaswamy et al.
patent: 6539025 (2003-03-01), Manning et al.
patent: 6650641 (2003-11-01), Albert et al.
patent: 6907001 (2005-06-01), Nakayama et al.
patent: 7016367 (2006-03-01), Dyckerhoff et al.
patent: 2001/0023469 (2001-09-01), Jeong et al.
patent: 2002/0136230 (2002-09-01), Dell et al.
patent: 2002/0176431 (2002-11-01), Golla et al.
patent: 2005/0018682 (2005-01-01), Ferguson et al.
Bennett, Jon C. R., “Packet Reordering is Not Pathological Network Behavior,” Dec. 1999, pp. 789-798, vol. 7, No. 6, IEEE/ACM Transactions on Networking.
Adiseshu, Hari, Parulkar, Guru and Varghese, George, “A Reliable and Scalable Striping Protocol,” 11 pages, Department of Computer Science, Washington University, St. Louis, MO, “The referenced paper is to appear inComputer Communication Review, a publication of ACM SIGCOMM, vol. 26, No. 4, Oct. 1996. ISSN #0146-4833,” according to ACM SIGCOMM '96 paper retrieval site, Retrieved from the Internet Jan. 15, 2003 <http://www.acm.org/sigcomm/sigcomm96/papers/adiseshu.html>, attached.
Shreedhar, M., Varghese, G., “Efficient Fair Queuing Using Deficit Round Robin”, pp. 231-242, SIGCOMM '95, Cambridge, MA, U.S.A.
D. Shah and P. Gupta, “Fast incremental updates on Ternary-CAMs for routing lookups and packet classification,” in Proc. of Hot Interconnects-8, Stanford, CA, USA, Aug. 2000.
Bambos Nicholas
Belur Harish
Devanagondi Harish
Heaton Richard
Torabi Majid
Chan Wing
Cho Hong Sol
Greenfield Networks, Inc.
Needle & Rosenberg P.C.
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