Queueing architecture and load balancing for parallel packet...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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C370S429000

Reexamination Certificate

active

07317730

ABSTRACT:
A parallel packet processing queueing architecture and method are described. A packet is divided up into cells. A first or start processor queue is selected for the first cell. The following cells of the packet are then placed in the queues in a predetermined order. An example of a predetermined order is placing the cells in consecutive processor queues modulo (the number of processor queues) after the start processor. Such a predetermined order is illustrated in the context of a per Cell Contiguous Queueing (CCQ) architecture. The architecture provides benefits of alleviating the pre-processing and post-processing buffering burdens and decreasing the amount of information required for reassembly of the packet.

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