Queued interrupt mechanism with supplementary command/status/mes

Details Queued interrupt mechanism with supplementary command/status/mes Queued interrupt mechanism with supplementary command/status/mes

1992-09-29

1994-06-07

Evans, Arthur G.

395425, G06F 1324

Patent

active

053197534

ABSTRACT:
A bidirectional interrupt technique and mechanism is described for handling programmable length interrupt messages between two devices, preferably both processors, through dual, programmably defined memory queues. The technique and mechanism automatically updates a read and write address counter, a queue count register, and an interrupt count register for each direction of the flow of interrupts.

REFERENCES:
patent: 4005391 (1977-01-01), MacPherson
patent: 4275440 (1981-06-01), Adams, Jr. et al.
patent: 4400773 (1983-08-01), Brown et al.
patent: 4438489 (1984-03-01), Heinrich et al.
patent: 5133056 (1992-07-01), Miyamori
patent: 5195864 (1993-02-01), Bonevento et al.

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