Queue design system supporting dependency checking and issue...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...

Reexamination Certificate

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Reexamination Certificate

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07831808

ABSTRACT:
A processor includes a general purpose (GP) unit adapted to receive and configured to execute GP instructions; and includes a single instruction multiple data (SIMD) unit adapted to receive and configured to execute SIMD instructions. An instruction unit comprises a first logic unit coupled to the GP unit and a second logic unit coupled to the SIMD unit, wherein SIMD instructions are processed subsequent to GP instructions. In the first logic unit a GP instruction with unresolved dependencies unconditionally causes subsequent SIMD instructions to stall, and an SIMD instruction with unresolved dependencies does not cause subsequent GP instructions to stall. The first logic unit resolves dependencies in GP instructions, provides dependency-free instructions to the GP unit, and provides SIMD instructions to the second logic unit. The second logic unit resolves dependencies in SIMD instructions and provides dependency-free instructions to the SIMD unit.

REFERENCES:
patent: 5978838 (1999-11-01), Mohamed et al.
patent: 6742111 (2004-05-01), Soni
Espasa et al.; “Out-of-Order Vector Architectures”; 1997; IEEE Computer Society; International Symposium on Microarchitecture '97; pp. 160-170.

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