Queue apparatus and mechanics for a communications interface arc

Details Queue apparatus and mechanics for a communications interface arc Queue apparatus and mechanics for a communications interface arc

1992-04-16

1995-01-31

Richardson, Robert L.

G06F 1300

Patent

active

053865146

ABSTRACT:
A communication interface between a port driver and an port adapter of a host computer includes a singly-linked queue resident in a host memory of the computer. The queue includes a header element and a stopper element with message entries linked therebetween. The message entries contain information to be exchanged between the port driver and port adapter. Each message entry includes at least a carrier that contains a forward link pointer to the next entry in the queue and message/response specific control information. The stopper element identifies the end of the queue and is distinguishable from a message entry by a valid indicator, e.g., the state of at least one bit of the forward link pointer. Functionally, the stopper entry allows the port driver and port adapter to concurrently insert and remove message entries of the singly-linked queue in a reliable manner without the use of any external synchronization mechanism.

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Publication, "CSR Architecture (DMA Processors), and Optional Framework for DMA-Processors Architectures" draft 1.0 by P1212 Working Group of the Microprocessor Standards Committee, Standards Subcommittee of the Technical Committee on Microprocessor and Microcomputers of the IEEE Computer Society, Jan. 31, 1990 at pp. 4-12.
Collier et al., "Queued Communication Interface"; IBM Techical Disclosure Bulletin vol. 19, No. 1, Jun. 1976, New York, US pp. 217-221.

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