Static information storage and retrieval – Powering – Conservation of power
Patent
1977-04-20
1978-10-10
Hecker, Stuart N.
Static information storage and retrieval
Powering
Conservation of power
365190, G11C 700
Patent
active
041200470
ABSTRACT:
This disclosure relates to an MOS or FET memory array that uses a single voltage source (i.e., 5 volts) and operates basically as a static memory array rather than as a dynamic memory array that requires the gates of the MOS devices of the memory array to be periodically refreshed to restore or refresh the memory states contained therein. Each of the memory cells of the memory array contains four MOS devices that are cross-coupled into a flip-flop type of memory cell. All of the memory cells connected to a common word line are also connected to a common return line to which is connected a single resistor and a single large MOS or FET device. The large MOS device is turned on during the active operation of the memory array (during write and read operations) and is turned off during the standby operation of the memory array. The resistor functions to insure that some current flow takes place, during the standby operation, from all the memory cells connected to the common return line in order to maintain the data states ("1" or "0") in each of the memory cells.
REFERENCES:
patent: 3703710 (1972-11-01), Kubo et al.
Palfi, Bilevel Powered FET Memory Cell, IBM Technical Disclosure Bulletin, vol. 14, No. 1, 6/71, pp. 261-262.
Gladu et al., Multigated "Dribble" Powered MOS FET Storage Cell, IBM Technical Disclosure Bulletin, vol. 17, No. 11, 4/75 p. 3336.
Wiedmann, Memory Cell with Low-Standby Power, IBM Technical Disclosure Bulletin, vol. 14, No. 6, 11/71, p. 1720.
Hecker Stuart N.
National Semiconductor Corporation
Weiss Harry M.
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