Quasi-passive switched-capacitor (SC) delay line

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform

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327278, H03H 1126

Patent

active

054537100

ABSTRACT:
A quasi-passive switched capacitor (SC) delay line includes a predetermined number (N) of passive SC delay stages and an amplifier. Each delay stage includes a first transistor having a control terminal for receiving a clock phase, an input terminal for receiving an input signal, and an output terminal, a second transistor having a control terminal for receiving a different clock phase, an input terminal connected to the output terminal of the first switching device, and an output terminal coupled to the amplifier input, and a capacitor coupled between the output terminal of the first transistor and a common supply voltage. The control terminal of each first transistor receives a unique clock phase and the control terminal of the second transistor of the same stage being receives a different clock phase wherein the clock phase received by the second transistor is delayed by two clock cycles from the clock phase received by the first transistor. The resulting quasi-passive SC delay line produces a delay equal to (N-2).times.T, where N is equal to the number of delay stages and T is equal to the pulse width of the clock phases.

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Hughes, John B. and Moulding, Kenneth W., IEEE Journal of Solid-State Circuits, vol. 28, No. 3, Mar. 1993, Switched-Current Signal Processing for Video Frequencies and Beyond, pp. 314-322.

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