Quasi-differential successive-approximation structures and...

Details Quasi-differential successive-approximation structures and... Quasi-differential successive-approximation structures and...

2001-02-26

2002-06-04

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S150000, C341S163000

Reexamination Certificate

active

06400302

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to successive approximation register analog-to-digital converters (SAR ADCs).
2. Description of the Related Art
The conventional SAR ADC
20
of
FIG. 1
comprises a sampler
22
that is coupled to a switched capacitor (or charge distribution) digital-to-analog converter (CDAC)
24
, a successive approximation register (SAR)
26
, a comparator
28
that is coupled between the CDAC
24
and the SAR
26
and a timing and control module
30
that is coupled to the sampler
22
and the SAR
26
.
The CDAC includes an array of capacitors whose capacitances are binarily weighted. For example, a most-significant capacitor has a capacitance C/2, a next most-significant capacitor has a capacitance C/4and so on. The least-significant capacitor has a capacitance of C/2
n
and is duplicated by a capacitor
31
so that the total array capacitance is C. Accordingly, binary division is realized when each capacitor's capacitance is successively compared to the array capacitance (e.g., as a capacitive divider, capacitance C/2 is ½ that of the array capacitance C, capacitance C/4 is ¼ that of the array capacitance and so on).
The capacitor top plates (e.g., the top plate
32
) are coupled to one differential port
33
of the comparator
28
and their bottom plates (e.g., the bottom plate
34
) are selectively coupled through bottom-plate switches
35
to a sample (IN) from the sampler
22
, to a first reference signal which is generally that applied to the comparator's other differential port
36
(e.g., GND) and to a second reference signal (REF) which is generally the full scale range of the SAR ADC
20
. The bottom-plate switches
35
respond to control signals
37
from the SAR
26
which also controls an output switch
38
that selectively causes the CDAC's analog output signal to be coupled to the comparator
28
or to ground.
In operation of the SAR ADC, an analog signal is presented to the input port
39
of the sampler (e.g., a sample-and-hold amplifier (SHA)) and, in response to a hold signal from the timing and control module, the sampler provides an input signal sample S
in
to the input port (IN) of the switched capacitor DAC
24
. Initially, the output switch
38
applies a ground to all of the top plates
32
and the bottom-plate switches
35
couple the input signal sample S
in
to all of the bottom plates
34
so that all capacitors acquire a potential of S
in
. Subsequently, the SAR causes the output switch
38
to couple the top plates
32
to the comparator's differential port
33
and the switches
35
to couple the bottom plates
34
to GND so that a potential−S
in
appears at the comparator's differential port
33
.
The SAR
26
then causes the bottom plate of the capacitor C/2 to be switched to REF and a capacitive divider ratio of (C/2)/C changes the potential at the differential port
33
to REF/2−S
in
. This latter signal is illustrated in the diagram
40
of FIG.
2
A. If the comparator output indicates that REF/2−S
in
is below GND, the SAR leaves the bottom plate of capacitor C/2 coupled to REF. If the comparator output indicates that REF/2−S
in
is above GND (as in FIG.
2
A), the SAR returns the bottom plate to GND. This process is repeated with the next capacitor C/4 which changes the potential at the differential port
33
to REF/4-S
in
.
FIG. 2A
illustrates that REF/4−S
in
is less than GND so that the SAR leaves the bottom plate of capacitor C/4 coupled to REF.
This process is repeated for the remaining capacitors to complete a successive approximation sequence that causes the potential on the top plates to approximate the potential at the comparator's other differential port
36
(i.e., GND) and thereby causes the control signals
37
to become a binary weighted version of the input sample S
in
. That is, the control signals form a successive approximation word that corresponds to the input sample S
in
and is delivered over a digital output bus
41
. The conversion process may be controlled through a control bus
42
that couples the timing and control module
30
to external components. Because the above-described operation is based upon successive approximation words from the SAR, this type of ADC is generally referred to as a SAR ADC.
A principal advantage of CDACs is that their accuracy and linearity are primarily determined by photolithography which defines capacitor plate areas to thereby establish capacitances and capacitance matching. In addition, small calibration capacitors can be added and switched under control of the SAR
26
to improve accuracy and linearity and eliminate the need for ADC trimming routines (e.g., thin-film laser trimming). CDACs also reduce static currents and DC power dissipation and provide a high degree of temperature stability because the temperature tracking between switched capacitors is typically quite high (e.g., better than 1 ppm/° C.).
The SAR ADC
20
is an example of a single-ended SAR ADC configuration. In another single-ended configuration, the calibration capacitors are in the form of a second CDAC which is also coupled to the differential port
33
of the comparator
28
of FIG.
1
. The second CDAC provides analog correction signals that compensate for capacitance mismatches in the first CDAC
24
. The switches (e.g., metal-oxide semiconductor (MOS) switches) of single-ended SAR ADC configurations typically inject error charges into the comparator (
28
in
FIG. 1
) and these switching-induced errors are difficult to eliminate.
Accordingly, another conventional SAR ADC configuration adds a “dummy” CDAC and couples it to the comparator's other differential port (
36
in
FIG. 1
) and drives the dummy's capacitor array with a fixed reference (e.g., GND). This creates a pseudo-differential configuration which injects similar error charges into the differential input of the comparator so that the errors are substantially reduced by the common-mode rejection of the comparator. Because it adds a third CDAC, this pseudo-differential configuration requires substantial integrated circuit area.
Circuit area is reduced in a different pseudo-differential configuration in which the dummy CDAC at the other differential port (
36
in
FIG. 1
) provides the analog correction signals and accordingly, the second CDAC at the differential port
33
can be eliminated.
Pseudo-differential configurations reduce switching-induced errors but their signal-to-noise ratio (SNR) is less than desired. The SNR is substantially improved in a fully-differential configuration in which first and second CDACs are coupled differentially to the comparator and are both driven with successive approximation signals from the SAR so their analog signals to the comparator (
28
in
FIG. 1
) change in opposite and equal steps during the successive approximation sequence.
Exemplary differential signals are illustrated in the diagram
44
of
FIG. 2B
where REF/2−S
in
is compared to −REF/2+S
in
. Successively, REF/4−S
in
is compared to −REF/4+S
in
and so on. Because −REF/2+S
in
does not exceed REF/2−S
in
, the SAR returns the bottom plates of capacitors C/2 of the first and second CDACs to GND. In contrast, −REF/4+S
in
exceeds REF/4−S
in
, so that the SAR leaves the bottom plates of capacitors C/4 of the first and second CDACs coupled to REF.
In a fully-differential configuration, the sampler
22
of
FIG. 1
would have a differential input port
46
and the differential signals would vary from positive full scale of REF and GND respectively at the upper and lower sides of the port to negative full scale of GND and REF respectively at the upper and lower sides. The input signal range of a fully-differential configuration is therefore effectively doubled while noise has not been substantially changed so that the SNR is also substantially doubled. Because both CDACs are active in this fully-differential config

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