Quarter-square multiplier based on the dynamic bias current tech

Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – Combining of plural signals

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

327563, 327357, 327349, 330253, H03F 345

Patent

active

059091363

ABSTRACT:
A four-quadrant multiplier which is constructed from two squaring circuits using the quarter-square technique and is suitable for an integrated circuit (IC) or a large-scale integrated circuit (LSI). Each of the squaring circuits has a pair of differential input terminals, an output terminal and two differential pairs. Each of differential pairs is composed of first and second transistors whose sources or emitters are connected in common, receives a differential input voltage impressed between the differential input terminals. In each differential pair, a constant current source of a predetermined current value and an dynamic bias current source are inserted in parallel between the common sources or the common emitters and the grounding point. The dynamic bias current source is realized by a current mirror circuit which outputs current equal to the drain current or the collector current of the second transistor. Therefore, the tail current of each differential pair is current given by the sum of the output current of the second transistor and the predetermined constant current. The output current of each squaring circuit is represented by the sum of the drain currents or the collector currents of the second transistors of both of the differential pairs.

REFERENCES:
patent: 4965528 (1990-10-01), Okanobu
patent: 5107150 (1992-04-01), Kimura
patent: 5151625 (1992-09-01), Zarabadi et al.
patent: 5187682 (1993-02-01), Kimura
patent: 5357149 (1994-10-01), Kimura
patent: 5381113 (1995-01-01), Kimura
patent: 5438296 (1995-08-01), Kimura
patent: 5481224 (1996-01-01), Kimura
patent: 5485119 (1996-01-01), Kimura
patent: 5500623 (1996-03-01), Kimura
patent: 5523717 (1996-06-01), Kimura
patent: 5552734 (1996-09-01), Kimura
patent: 5576653 (1996-11-01), Kimura
patent: 5578965 (1996-11-01), Kimura
patent: 5581210 (1996-12-01), Kimura
"Microelectronic Circuits", Sedra and Smith, third edition, pp. 220-223 and 308-312, 1991.
"CMOS Temperature-Stable Linearised Differential Pair", Dias et al., Electronics Letters, vol. 28, No. 25, Dec. 1992.
"Linearity Improvement of CMOS Transconductors for Low Supply Applications", Chen et al., Electronics Letters, vol. 29, No. 12, Jun. 1993.
IEEE Journal of Solid-State Circuits,"Adaptive Biasing CMOS Amplifiers"; Degrauwe et al., vol. SC-17, No. 3, Jun. 1982.
"A Unified Analysis of Four-Quadrant Analog Multipliers Consisting of Emitter and Source-Coupled Transistors Operable on Low Supply Voltage"; IEICE Transactions on Electronics E76-c(1993) May, No. 5, Katsuji Kimura, May 1993.
Katsuji Kimura, "A Dynamic Bias Current Technique for a Bipolar Exponential-Law . . . Supply Voltage", IEICE Trans. Fundamentals, vol. E77-A, No. 11, Nov., 1994, pp. 1922-1928.
Katsuji Kimura, "A Unified Analysis of Four-Quadrant . . . Operable on Low Supply Voltage", IEIEE Trans. Electronics, vol. E76-C, No. 5, May, 1993, pp. 714-738.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Quarter-square multiplier based on the dynamic bias current tech does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Quarter-square multiplier based on the dynamic bias current tech, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Quarter-square multiplier based on the dynamic bias current tech will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-957275

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.