Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis
Reexamination Certificate
2000-12-11
2004-06-22
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With specified crystal plane or axis
C257S618000, C257S622000
Reexamination Certificate
active
06753593
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an improved structure for a transistor and methods for providing such a transistor.
2. Discussion of Prior Art
Over the last two decades there has been much interest in semiconductor devices which operate by restricting the motion of current carriers in one or more directions. In such devices the carriers can only occupy a discrete set of energy levels or sub-bands in one or more dimensions. The motion of the carriers is said to be quantised in the direction of confinement.
In heterojunctions, formed by the joining together of two semiconductor compounds of different band gaps, the carriers are confined to a potential or quantum well. A two dimensional electron gas is formed if the carriers are electrons (or a two dimensional hole gas is formed if the majority carriers are holes).
One particular type of semiconductor device which has been fabricated, typically from GaAs, is the single electron transistor (SET) which was invented in 1987. In this device the two dimensional electron gas is further confined by external gates to form a so called quantum dot which is of such a size that it can hold only a few electrons (typically between 0 and 20). Furthermore, once this number is fixed (by an external contact potential) it does not fluctuate in time by more than one electron.
Such devices are traditionally confined to operate at low temperatures (typically less than liquid nitrogen temperatures) due to the physics which allows them to function. The devices rely on the fact that the quantum dot has a small capacitance, and the energy required to add or remove electrons is quite large. If the device is cooled to low temperatures the electron thermal energy becomes less than the charging energy. Without a significant source-drain voltage bias the electrons cannot travel through the quantum dot. That is, the capacitance of the dot is so small that the addition of a single electron to the potential well significantly increases the electrostatic energy. This is known as Coulomb blockade which suppresses current flow for all gate voltages except to certain values at which the energy of N and N+1 electrons in the quantum dot is approximately the same.
SUMMARY OF THE INVENTION
It is an ongoing aim to increase the operating temperature of quantum devices. One method of achieving this is to attempt precise patterning and etching of structures to provide further confinement of the two dimensional electron gas. However, this requires much smaller dimensions and also greater dimensional uniformity than can be realised by traditional lithography and etching. The skilled person will appreciate that using standard optical lithography feature sites of substantially 0.1 &mgr;m and registration of substantially ±0.3 &mgr;m are achievable. Moving to e-beam lithography the feature sizes decrease to 30 nm with a registration of 100 nm.
According to a first aspect of the invention there is provided a transistor having at least one, substantially one-dimensional, elongate conducting means provided by at least a first semiconductor substantially surrounded by a second semiconductor and extending between source and drain electrodes, and in which there is provided at least one further gate electrode in a region of the elongate conducting means.
Such a transistor has the advantage that it is possible to provide confinement for the electrons on a much smaller scale than was previously obtainable. The transistor may be a single electron transistor (SET). The skilled person will appreciate that this is of fundamental importance for producing SETs which operate at higher temperatures; it is possible to reduce the capacitance of the dot by reducing the dimensions of the dot. An electron gas is “hard” confined in two dimensions by the conducting means.
The conducting means may be provided in a bottom region of a groove. This technique allows the conducting means to be fabricated with smaller dimensions than is possible with lithography techniques.
The first semiconductor may be gallium arsenide (GaAs). The second semiconductor may be aluminium gallium arsenide (AlGaAs). As the skilled person will appreciate these materials are particularly suitable since they are relatively well lattice matched and have a suitably large band gap difference. However, other material systems may equally be possible. For instance indium antimonide (InSb) may be suitable, possibly with gallium nitride (GaN), or possibly with aluminium nitride (AlN).
In one embodiment a groove is formed into a substrate, which may be the same material as the first semiconductor and has a region of the second semiconductor, provided at the base of the groove, and on the sides of the grooves lining the groove. The conducting means may comprise an elongate region of the first semiconductor in a bottom region of the second semiconductor, that is in a bottom region of the lined groove. A layer of a third semiconductor may be provided on top of the first semiconductor. This provides a convenient structure for providing the two dimensional hard confinement. The skilled person will appreciate that this structure could be used with the material systems discussed above. The second and third semi conductors may be substantially the same materials, providing a convenient way of surrounding the first semiconductor with the second.
An anti-oxidation layer may be provided associated with (e.g. on top of) the third semi-conductor layer to prevent oxidation of the third semi-conductor layer. The anti-oxidation layer may be the same material as the first semiconductor. That is the anti-oxidation layer may be GaAs.
The region of the first semiconductor (possibly GaAs) in the bottom of the second semiconductor lined groove may be thought of as a quantum wire. If the wire is sufficiently short, and free from impurities, quantised conduction steps may be seen, which would be indicative of one dimensional conduction. However, fluctuations in the thickness of the wire may be provided and give rise to Coulomb blockade. This Coulomb blockade would give single electron transistor action. In the embodiment where quantised conduction occurs transistor action may also be achievable by the provision of gate structures to provided segregation of the wire into one or more quantum dots. Indeed, multiple gates may be provided to achieve multiple quantum dots. The skilled person will appreciate that prior art transistors generally have 2-dimensional or 3-dimensional conducting means. In the context of this description a 1-dimensional conducting means may be thought of as a wire rather than as a plane, or box.
Preferably the groove is provided within a top region of a mesa structure projecting from a substrate, providing a convenient way of isolating the v-groove from the substrate.
There may be provided more than one conducting means. These may be provided substantially horizontally next to one another and possibly substantially parallel to each other. Alternatively, or additionally, these may be provided substantially vertically above one another. Indeed, a two dimensional grid of conducting means may be provided. Providing more than a single conducting means can have a number of advantages including: it can increase the maximum current handling capability of the device; it can increase the tolerance of the device to defects within the manufacturing process/materials used (The skilled person will appreciate that during crystal growth and device processing defects occur. Having more that a single conducting member can increase the tolerance to these defects); the tolerance of random events, such as photon interactions, can also be increased.
The skilled person will appreciate that the gate electrodes provide soft confinement within the conducting means and effectively provide a quantum dot. There may be provided a plurality of quantum dots along the conducting means. A plurality of dots can be advantageous for a number of reasons. For instance, it has been found that when providing a transistor fro
Jefferson John H
Phillips Timothy J
Flynn Nathan J.
QinetiQ Limited
Quinto Kevin
LandOfFree
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