Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Patent
1998-02-12
2000-07-18
Mintel, William
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
257 25, 257 27, 257401, 257408, H01L 2906, H01L 310328, H01L 310336
Patent
active
060910763
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a MOS (Metal-Oxide-Semiconductor) quantum well transistor and processes for manufacturing it.
It has applications in microelectronics for manufacturing various devices, for example such as digital inverters that use MOS transistors complementary to each other.
STATE OF PRIOR ART
FIG. 1 shows a schematic cross-sectional view of a conventional MOS transistor at the end of the integration process of forming this transistor.
The transistor in FIG. 1 comprises a p type silicon substrate 2.
Two areas 4 and 6 separated from each other are formed on this substrate 2.
These areas 4 and 6 are n.sup.+ type diffused areas forming the transistor source and drain.
As can be seen in FIG. 1, areas 4 and 6 are prolonged by areas 8 and 10 respectively, which are type n.sup.- diffused areas (less doped than areas 4 and 6).
Areas 8 and 10 form extensions to the source and drain areas under the transistor grid that will be considered later.
The transistor in FIG. 1 also comprises two areas 12 and 14 that extend above areas 4 and 6 respectively, at approximately the same level as areas 8 and 10 (which face each other and are only separated from each other by a small p type silicon interval).
These areas 12 and 14 are made from a metal silicide and are self-aligned with the transistor grid and with the field insulation areas in this transistor, which will be considered later.
Areas 12 and 14 form the metallizations-shunts of the transistor source and drain.
Above the p type silicon area 16 separating areas 8 and 10 from each other, there is an electrically insulating layer 18 made of silica which also extends above these areas 8 and 10 and which forms the transistor grid insulation.
There is a layer 20 of polycrystalline silicon above layer 18.
There is a layer 22 above this layer 20, made of a metal silicide and forming a metallization-shunt.
The transistor grid is formed by these two layers 20 and 22.
Furthermore, two electrically insulating spacers 24 and 26, for example made of silica or silicon nitride, extend on each side of the stack formed by the layers 20 and 22 until the grid insulation 18.
The transistor shown in FIG. 1 is electrically insulated from other identical transistors (not shown) also formed on substrate 2 by means of LOCOS type field insulation areas 28 and 30.
The entire structure thus obtained is covered by an insulating layer 32 made of silica glass doped with phosphorus and boron.
Two openings pass entirely through this layer 32 and open up into areas 12 and 14 respectively.
These two openings are filled with a metal by chemical vapor deposition and form the source and drain contacts 34 and 36 respectively.
The transistor in FIG. 1 also comprises two metallic interconnection layers 38 and 40 located on the surface of the layer 32 and prolong contacts 34 and 36 respectively.
The grid contact is not shown in FIG. 1.
FIG. 2 is a schematic cross-sectional view of another conventional MOS transistor.
It is a MOS transistor on SOI (Silicon On Insulator), shown at the end of its integration process.
The transistor in FIG. 2 is different from the transistor in FIG. 1 in that layers 4 and 6 are much thinner, and that these layers 4 and 6 and the silicon area 42 between these layers are supported on a thick layer 44 of buried silica that is itself supported on a silicon substrate 46.
Another quantum dot MOS transistor is known in the following reference document:
(1) Silicon single hole quantum dot transistor for complementary digital circuits, E. Leobandung, L. Guo and S. Y. Chou, IEDM 95, p 367 to 370.
In this transistor described in document (1), the grid is added on after the source and drain areas are made.
The size of this known transistor is such that its electrical behavior is not entirely related to the behavior of the quantum well included in this transistor.
In fact, this known transistor comprises a channel with small dimensions between the transistor source and drain, but the grid added onto the source and drain is large in proportion.
This is a disadvant
REFERENCES:
patent: 4712122 (1987-12-01), Nishizawa et al.
patent: 5198879 (1993-03-01), Ohshima
patent: 5608231 (1997-03-01), Ugajin et al.
patent: 5731598 (1998-03-01), Kado et al.
patent: 5783840 (1998-07-01), Randall et al.
patent: 5796119 (1998-08-01), Seabaugh
patent: 5831294 (1998-11-01), Ugajin
Commissariat a l''Energie Atomique
Mintel William
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