Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Reexamination Certificate
1998-11-09
2003-12-23
Baumeister, B. William (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
C257S012000, C257S622000, C257S628000, C438S962000
Reexamination Certificate
active
06667492
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to nanometer scale structures formed on substrates.
2. Description of the Prior Art
With the decreasing size of integrated circuits (ICs), problems having been encountered in trying to produce narrower and narrower structures in a piece of silicon or other semiconductor material. For example, in order to reduce the minimum size of the structures on integrated circuits by an order of magnitude below their current size of about 2000 Å, it is generally believed that the current methods for producing patterns on semiconductor wafers using optical techniques will have to be abandoned.
One method that has been proposed to create small structures on integrated circuits is to use special masks made by electron beam lithography and then to use X-rays to expose the patterns for the integrated circuits. However, there are severe drawbacks to using X-rays, including the fact that conventional masking materials and photoresists may not be used. More importantly, the minimum geometry that may be produced is probably no better than about 700 Å.
Therefore, there exists a need for a method for forming nanometer sized structures that may be used to greatly reduce power consumption and increase operating speeds of integrated circuits. If those large improvements may be made using current optical lithography in conjunction with a method to form well-controlled nanometer sized structures in critical areas of devices in integrated circuits, then the advantages would be immense.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide useful quantum structures whose smallest meaningful dimensions are about two orders of magnitude smaller than the smallest dimensions now being produced on modern integrated circuits in production.
The resulting structures amount to a radically new kind of material, and as such there are many applications extending from electronics to physics to biology and chemistry. The present invention provides a new form of “atomic lithography” that amplifies the existing surface morphology and crystal structure itself to establish line and space distances. No electromagnetic or charged particle beams need be involved so there are no wavelength considerations. Furthermore, there is no chemical development in the traditional sense, although standard optical lithography may still be used to complete other components integrated circuits or other products.
According to one aspect of the present invention, there is provided a quantum ridge product comprising a substrate having a plurality of substantially parallel quantum ridges on a surface thereof, each pair of adjacent quantum ridges of the plurality quantum ridge having a pitch of 5.4 to 600 Å and being separated by a groove having a width of up to 597 Å and a depth of 4 to 30,000 Å, except ridge pitches from 5.4 to 9.3 Å will support quantum wires but will not support stable grooves to be etched in Silicon (Si). All the ranges refer to Si and must be increased or decreased by up to 30% for other crystals.
According to a second aspect of the present invention, there is provided a quantum ridge product comprising: a substrate having a plurality of substantially parallel quantum ridges on a surface thereof, each pair of adjacent quantum ridges of the plurality quantum ridge having a pitch of 5.4 to 600 Å, and ridges with pitches of 9.4 Å or larger being separated by a groove having a width of up to 597 Å, at least one of the quantum ridges having a quantum wire supported on top of at least one of the quantum ridges and extending in a direction along the length of the quantum ridge, the quantum wire comprising a conductive material having a width of 3 to 594 Å.
According to a third aspect of the present invention, there is provided a quantum tip product comprising a substrate having a plurality of quantum tips on a surface thereof, each of the plurality of quantum tips being separated from an adjacent quantum tip by grooves, each of the grooves having a width of up to 597 Å and a depth of 4 to 30,000 Å.
According to a fourth aspect of the present invention there is provided a quantum tip product comprising a substrate having a plurality of quantum tips on a surface thereof, each of the plurality of quantum tips being separated from adjacent quantum tips by grooves, each of the grooves having a width of up to 597 Å, at least one of the quantum tips having a quantum dot supported on top of at least one quantum tip, the quantum dot comprising a conductive material having a width of 3 to 594 Å.
According to a fifth aspect of the present invention, there is provided a method for making a quantum structure product comprising the steps of: providing a first substrate having a (
1
1
X) surface structure and including a plurality of substantially parallel quantum ridges and grooves on a surface thereof, the grooves having a width of up to 597 Å and separating adjacent quantum ridges; and coating the first substrate with a metal to form at least one quantum wire on at least one of the quantum ridges, the at least one quantum wire having a width of 3 to 47 Å.
According to a sixth aspect of the present invention, there is provided a quantum ridge product comprising two quantum ridge substrates bonded to each other, each of the substrates having a plurality of substantially parallel quantum ridges on a surface thereof, each pair of adjacent quantum ridges of the plurality quantum ridge having a pitch of 5.4 to 600 Å and being separated by a groove having a width of up to 597 Å and a depth of 4 to 30,000 Å, the quantum ridge substrates being bonded together at the quantum ridge surface of each substrate.
According to a seventh aspect of the present invention, there is provided a quantum ridge product comprising: a substrate having a plurality of substantially parallel quantum ridges on a surface thereof, each pair of adjacent quantum ridges of the plurality quantum ridges having a pitch of 5.4 to 600 Å and being separated by a groove having a width of up to 597 Å, at least one of the quantum ridges having a quantum dot supported on top of the at least one quantum ridge, the quantum dot comprising a conductive material having a width in at least one direction of 3 to 594 Å.
According to a tenth aspect of the present invention, there is provided a quantum structure product comprising a substrate including a groove having a width of up to 597 Å and a depth of 4 to 30,000 Å.
There are three general ranges for the pitches of the present invention. For the Self Aligned Atomic Shadowing (SALAS) procedure, the range is preferably 5.4 to 54 Å for quantum wires and quantum dots, and is 9.4 to 54 Å for SALAS when grooves are etched or when quantum tips or dots are produced. The range of pitches for the Self Aligned Atomic STEPS (SALASTEPS) is typically 54 to 600 Å. It should be appreciated that there is some overlap between the ranges of SALAS and SALASTEPS. The SALASTEPS pitches and local separations are somewhat variable due to the ragged single layer and double layer atomic steps, but the SALAS ridges are atomically straight and precisely spaced on the (
1
1
4
) surface of Si. The SALAS ridges on the (
5
5
12
) and other (
1
1
X) surfaces may have restructuring faults, but the ridges are atomically straight over long distances.
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Baumeister B. William
Jagtiani & Guttag
Kendall Don L.
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