Quantum dot memory cell

Details Quantum dot memory cell Quantum dot memory cell

1997-09-03

1999-07-13

Guay, John

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

257 14, 257316, 257321, 257 20, 257 17, 36518501, H01L 2906, H01L 2916, H01L 29788

Patent

active

059230460

ABSTRACT:
A channel layer and a spacer layer form a heterojunction therebetween. A V-shaped groove is formed in the spacer layer. The sharp bottom of the V-shaped is located above the heterojunction interface. On the bottom of the V-shaped groove a plurality of quantum dots are formed in a line and discretely. A gate electrode is formed above the quantum dots. A source electrode is connected to the heterojunction interface to form an ohmic contact therebetween. A drain electrode is connected to the heterojunction interface to form an ohmic contact therebetween. The quantum dots are arranged between the source and drain electrodes.

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patent: 5670790 (1997-09-01), Katoh et al.
patent: 5679962 (1997-10-01), Kizuki
patent: 5714766 (1998-02-01), Chen et al.
Guo, et al., "Single-Electron MOS Memory with Nanoscale Floating-Gate and Narrow Channel," IEDM-1996, pp. 955-956.
Nakajima, et al., "Room Temperature Operation of Si Single-Electron Memory with Self-Aligned Floating Dot Gate," IEDM-1996, pp. 952-953.
K. Yano, et al., "Room-Temperature Single-Electron Memory", IEEE Transactions on Electron Devices, vol. 41, No. 9, Sep. 1994, pp. 1628-1637.
S. Tiwari, et al., "A Silicon Nanocrystals Based Memory", Appl. Phys. Lett., vol. 68, No. 10, Mar. 4, 1996, pp. 1377-1379.

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