Semiconductor device manufacturing: process – Quantum dots and lines
Reexamination Certificate
1998-03-09
2001-07-24
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Quantum dots and lines
C438S022000, C438S034000, C438S035000, C438S036000
Reexamination Certificate
active
06265329
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to devices that operate through the conduction of a very small number of electrical carriers and to methods of fabricating, and controlling the fabrication of, the devices.
2. Background of the Invention
A relatively recent development in material science has been the ability to fabricate structures that are small on a quantum scale. On this small scale, 200Å or less, the applicable physics is neither that of the solid state bulk nor that of the gaseous-free atom, but rather that of a quantum-confined intermediate. Early in the development, these small-scale structures were formed in layers with confinement in one dimension only. The confined structures are typically composed of thin layers produced by MBE equipment on GaAs or other active substrates.
As an example of a use of these thin layers, lasers have been made that utilize the quantum confinement layers for carrier confinement or refractive optical confinement. In quantum-mechanically confined nano-structures, the degree of freedom in the free-electron motion decreases as N, the number of confined dimensions, goes up. This change in the electronic density of states has long been predicted to increase efficiency and reduce temperature sensitivity in lasers, and has been demonstrated for N=1 and 2. The techniques for the production of very thin layers of material with reasonable electronic mobilities require very meticulous crystal growth and exceedingly high purity.
For the ultimate case of N=3, there is also the occurrence of Coulomb blockade, a phenomenon that provides the basis for the operation of single-electron devices. Generally, a 3-D confined nano-structure is a small particle of material, e.g., semiconductor material, that is small enough to be quantum confined in three dimensions. That is, the quantum-contained particle has a diameter that is only about 200Å or less. This creates a three-dimensional well with quantum confinement in all directions.
Traditionally, attempts to fabricate 3-D confined nano-structures relied on e-beam lithography. More recently, STM/AFM and self-assembled quantum dots (3-D confined nano-structures) have been fabricated. However, incorporating the 3-D confined nano-structures into a useful device is very difficult and has not been accomplished in a manufacturable process.
Accordingly, it would be very beneficial to be able to efficiently manufacture 3-D confined nano-structures in a useful device.
It is a purpose of the present invention to provide 3-D confined nano-structures in a useful device.
It is another purpose of the present invention to provide a new and efficient method of manufacturing 3-D confined nano-structures.
It is still another purpose of the present invention to provide a new and efficient method of controlling the manufacture of 3-D confined nano-structures.
SUMMARY OF THE INVENTION
The above problems and others are at least partially solved and the above purposes and others are realized in a sparse-carrier device including a crystal structure formed of a first material and including a crystallographic facet having a length, a first width and a second width, and quantum dots formed of a second material and positioned on the crystallographic facet, the quantum dots extending along the length of the crystallographic facet in a first distribution pattern along the first width and a second distribution pattern along the second width. In a specific embodiment, the first width is greater than the second width wherein the first distribution pattern correspondingly includes a greater number of dots than the second distribution pattern. In another embodiment, the first width is less than the second width wherein the first distribution pattern correspondingly includes a lesser number of dots than the second distribution pattern. The quantum dots, and the varying distribution patterns of quantum dots located in the first and second widths of the crystallographic facet, form a building block for circuits based on sparse or single electron devices. Generally, electrical connections may be provided to the quantum dots for the passage of electrical carriers or the propagation of changes in polarization states therealong, depending upon the operation.
Consistent with the foregoing, associated methods may also be provided.
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“Positioning of InAs Quantum Dots on Sub-250 Facets using Selective Area Epitaxy”, Tsui, p. 531-534, 1998, IEEE Journal of Quantum Electronics.
Shiralagi Kumar
Tsui Raymond K.
Goodwin David
Koch William E.
Motorola Inc.
Parsons Eugene A.
Wilczewski Mary
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