Electrical computers and digital processing systems: processing – Processing architecture
Patent
1998-04-09
2000-06-27
Coleman, Eric
Electrical computers and digital processing systems: processing
Processing architecture
712 32, G06F 1710
Patent
active
060818824
ABSTRACT:
A process and apparatus for quantum acceleration of a conventional computer by coupling a few quantum devices to the conventional computer. Initially, a first, second, and third maximally entangled qubit are prepared in a Greenberger-Horne-Zeilinger state. A fourth qubit is prepared in a perfect superposition of states which is unentangled from the three qubits. The second qubit is then measured and its measured value is input to the conventional computer. The conventional computer operates on this measured input value and performs an inverse oracle function. The second qubit is modified according to the output from the conventional computer. This modified qubit is used as one of two control inputs for controlling a quantum gate. The other control input is the fourth qubit. The quantum gate phase inverts the third qubit according to the two control inputs. A measurement of the complement of the first qubit is taken in order to produce the necessary quantum interference of the third qubit. The third qubit can now be measured to find the correct final solution. An N-bit quantum accelerated computer can be constructed by implementing N numbers of 4-qubit sets.
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Coleman Eric
Silicon Graphics Inc.
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