Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Subsequent separation into plural bodies
Reexamination Certificate
2011-01-18
2011-01-18
Smith, Zandra (Department: 2822)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Subsequent separation into plural bodies
C438S455000, C257SE27112
Reexamination Certificate
active
07871900
ABSTRACT:
A method for forming a structure is provided and includes implanting an atomic species into a donor substrate having an upper surface at a given depth relative to the upper surface to form an embrittlement zone in the donor substrate, the embrittlement zone defining a removable layer within the donor substrate. The method further includes assembling the upper surface of the donor substrate to a receiver substrate. Additionally, the method includes detaching the removable layer from the donor substrate at the embrittlement zone, thereby forming a detachment surface on the removable layer, by high temperature annealing. The high temperature annealing includes a temperature upgrade phase to a predetermined maximum temperature, maintaining the maximum temperature for a predetermined exposure duration, and a temperature downgrade phase. The maximum temperature and the exposure duration are selected so as to prevent the appearance of significant defects at the detachment surface.
REFERENCES:
patent: 2003/0216008 (2003-11-01), Schwarzenbach et al.
patent: 2004/0262686 (2004-12-01), Shaheen et al.
patent: 2005/0026426 (2005-02-01), Maleville et al.
patent: 2006/0040470 (2006-02-01), Ben Mohamed et al.
patent: 2006/0046431 (2006-03-01), Blietz et al.
patent: 1359615 (2003-11-01), None
patent: 1628339 (2006-02-01), None
patent: 2858462 (2005-02-01), None
patent: WO 2005/086228 (2005-09-01), None
G. Celler,Frontiers of Silicon-on-Insulator, Journal of Applied Physics, vol. 93, No. 9, pp. 4955-4978 (2003).
French Search Report of FR 0754131.
Bourdelle Konstantin
Nguyen Nguyet-Phuong
Schwarzenbach Walter
Novacek Christy L
S.O.I. TEC Silicon on Insulator Technologies
Smith Zandra
Winston & Strawn LLP
LandOfFree
Quality of a thin layer through high-temperature thermal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Quality of a thin layer through high-temperature thermal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Quality of a thin layer through high-temperature thermal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2689234