Data processing: measuring – calibrating – or testing – Measurement system – Performance or efficiency evaluation
Reexamination Certificate
1998-07-28
2001-03-13
Shah, Kamini (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system
Performance or efficiency evaluation
C702S035000, C702S081000, C702S082000, C700S109000, C700S222000, C700S121000
Reexamination Certificate
active
06202037
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a quality management system for a semiconductor device, and more particularly to a quality management system used in an in-line inspection.
2. Description of the Background Art
In order to increase and stabilize a yield of a semiconductor device, an inspection step is executed in a manufacturing line (in-line inspection) to observe the number of nonconformities (hereinafter referred to as “defects”) between a semiconductor device under manufacture and that on design, and if the number of defects exceeds a specified upper limit, the defects are probed and what is the defect source is estimated, to get rid of the defect source.
FIG. 7
is a conceptional diagram showing a manufacturing line of a semiconductor device and an in-line inspection executed therein. A process for manufacturing a semiconductor device needs over two hundred steps only for dealing a wafer, and it sometimes takes two months or more from start to finish. In such a case, with an inspection (quality evaluation) after completion, all products through the process that is the defect source during the past two months, at the worst, may have defects found in the inspection, if any, resulting in a serious damage. In order to suppress the damage to the least, the manufacturing process is divided into blocks, each consisting of associated steps, and the inspection (quality evaluation) is made on a block-by-block basis as shown in
FIG. 7
so that only two-or-three-days' damage is given if any defect is found. In
FIG. 7
, the manufacturing process is divided into blocks BLI to BLn and in-line inspection steps IE
1
to IEn are provided at the respective last stages of the blocks.
An outline of a prior-art in-line inspection will be discussed with reference to FIG.
8
. First, some of wafers through the last step of a block are taken into an inspection device
1
. As the inspection device
1
used may be an optical system utilizing intensity of scattered light for detection of defects, a mechanical system for mechanical detection of defects and the like. The inspection device of both types obtains measured data D
1
such as positional coordinates and size of the defects to be given to a quality management system S
90
for performing a quality management based thereon.
The quality management system S
90
has a measured-data judgment unit
4
for comparing the number of defects and the number of chips having a defect with predetermined values (upper control limit values). If the measured-data judgement unit
4
makes a judgment that the number of defects or the number of chips having a defect exceeds the respective upper limits of the predetermined values, the unit
4
gives a warning or an operation instruction CM
1
to associated apparatus
3
such as a semiconductor manufacturing apparatus.
As mentioned earlier, however, since the in-line inspection is made on a block-by-block basis for the semiconductor device through a plurality of (twenty to thirty) manufacturing steps, it is impossible to estimate what step causes the defect from only the data given by the inspection device
1
. For this reason, the wafer to be inspected is set in an observation device
2
to analyze an image of the defect in detail. The observation device
2
comprises a magnifying device such as an optical microscope and an electron microscope and magnifies a defective portion with the aid of the positional information of the defect given by the inspection device
1
, for observation.
The observation device
2
observes size and shape of the defect and condition of the defect and its periphery to thereby estimate what apparatus and process for manufacturing the semiconductor device may cause the defect (i.e., defect source) and give a warning or an operation instruction CM
2
to the associated apparatus
3
such as a semiconductor manufacturing apparatus, if necessary.
Since the quality management system S
90
as mentioned above is adopted in the prior-art in-line inspection, it is impossible to surely make a judgment of abnormal condition (deterioration in product yield) only because the number of defects or the number of chips having a defect exceeds the predetermined value.
Specifically, though an in-line inspection can detect a defect on a block-by-block basis and a probe can estimate the defect source, it is impossible to make a decision on what effect the defect has in all the steps, and in other words, whether the defect causes deterioration in product yield or not. Having a grasp of all the steps and knowing how an unsolved defect affects a final product makes it possible to make such a decision.
An human operator makes a judgment, from practical experience, on whether there is a defect that would cause deterioration in product yield, by observing defects one by one based on finding of defects on a block-by-block basis, and makes a decision on whether the manufacturing line should be stopped.
Therefore, it disadvantageously takes much time and labor from finding of defects to recognition of occurrence of abnormal condition in the conventional management system.
Further, the judgment from practical experience of a human operator on an influence degree (fatal or killer rate of the defect) has an accuracy problem as well as time and labor problems.
SUMMARY OF THE INVENTION
The present invention is directed to a quality management system for managing quality variance of a semiconductor device in a process of manufacturing the semiconductor device based on a design, by investigating defects of a semiconductor device under manufacture out of conformance with a design. According to a first aspect of the present invention, the quality management system comprises: first data processing means receiving first measured data on the defects outputted from a defect inspection device, for processing the first measured data to calculate first processed data including index values on the number and distribution of the defects; first processed-data judgment means receiving the first processed data, for making a judgment, based on a predetermined judgment condition, on whether a further investigation on the defects should be made or not; sampling means for sampling an object defect to be probed among the defects based on a predetermined sampling condition when it is judged that the further investigation should be made and outputting data on positional coordinates of the object defect to a defect analysis device; second data processing means receiving second measured data outputted from the defect analysis device as a result of analyzing the object defect based on the data on the positional coordinates, for processing the second measured data to calculate second processed data including index values at least on a shape of the object defect; and second processed-data judgment means receiving the second processed data, for automatically making an estimation, based on the second processed data, on what apparatus and process for manufacturing the semiconductor device may be a defect source.
According to a second aspect of the present invention, in the quality management system of the first aspect, the first measured data include at least one of the total number of defects in a unit of inspected area, area of each of the defects and area equivalent diameter, positional coordinates and indexes indicating size of each of the defects, the indexes indicating size being horizontal/vertical diameter, major axis and minor axis, the semiconductor device is one of a plurality of chips formed on a semiconductor wafer, the index values on the number and distribution of the defects include at least one of a first index value indicating the number of defects and the number of chips having the defects among the plurality of chips, a second index value indicating the number of defects within a predetermined size range and the number of chips having the defects among the plurality of chips within the predetermined size range, and a third index value indicating the number of defects in a p
Hattori Nobuyoshi
Tamada Tomoki
Yamana Kaoru
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Shah Kamini
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