Qualified non-overlapping clock generator to provide control lin

Details Qualified non-overlapping clock generator to provide control lin Qualified non-overlapping clock generator to provide control lin

1992-06-22

1994-04-26

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 328 63, 328 72, 377 78, H03K 513, H03K 700, H03K 1700, G11C 1900

Patent

active

053069625

ABSTRACT:
A clocking methodology for VLSI chips which uses global overlapping clocks, locally or remotely generated non-overlapping clocks, combined with pipeline control signals to generate signals which control the transfer gates of registers in a pipeline. The signals which control the transfer gates of the registers in a pipeline maintain the important timing relationships of the non-overlapping clock signals combined with the control signals. The global overlapping clocks are used where possible to provide timing advantages, while the non-overlapping clocks are used to eliminate race conditions as data propagates down a pipeline of transparent registers. Overlapping clock signals are used whenever such race conditions can be avoided, as at the ends of the registered pipeline, with the resultant performance improvement.

REFERENCES:
patent: 4827157 (1989-05-01), Machida et al.
patent: 4922137 (1990-05-01), Small et al.
patent: 4970405 (1990-11-01), Hagiwara
patent: 4999526 (1991-03-01), Dudley

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