Qualification of register file write enables using self-timed fl

Details Qualification of register file write enables using self-timed fl Qualification of register file write enables using self-timed fl

1992-06-16

1993-10-26

Malzahn, David H.

Boots, shoes, and leggings

364748, G06F 700

Patent

active

052572145

ABSTRACT:
A floating point processor in which floating point register file write enables are self-timed from the exception flags from the respective floating point processing units. This self-timing is achieved by forming the floating point processing units from self-timed logic gates which gate data in accordance with the values of the data itself. In other words, the output of a logic gate is made valid only when all inputs to the logic gate have been evaluated as being valid. Since the floating point exception signals from the floating point processing units are also self-timed and no longer edge triggered, the results of the floating point operation may be written to the register file on the same phase in which the result and the exception flags become valid, thereby allowing processing latency to be reduced by a state. Hence, if there is a floating point exception during a floating point operation, the register cell is not written. The floating point exception flags are also precharged to a true level and remain true until it is conclusively determined that a floating point exception will not result from the current floating point operation. At that time, the register cell is immediately written.

REFERENCES:
patent: 4961161 (1990-10-01), Kojima
patent: 5038313 (1991-08-01), Kojima
patent: 5201056 (1993-04-01), Daniel et al.
DeLano et al., "A High Speed Superscalar PA-RISK Processor" Proceedings of the Compcon Spring 1992, Digest of Papers, San Francisco, Calif.; Feb. 24-28, 1992.

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