Quadruply time-multiplex information bus

Details Quadruply time-multiplex information bus Quadruply time-multiplex information bus

1981-07-02

1984-10-23

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 930

Patent

active

044791780

ABSTRACT:
A quadruply time-multiplexed bus for digital processor systems. The quadruply time-multiplexed information bus is interfaced to a processor and an external memory to transfer addresses, data and program instructions between the processor and the external memory. The interface at the external memory includes the capability to store the addresses of extended bus or instructions being accessed. These stored addresses may be modified from the processor by the processor transmitting new addresses over the information bus or by having the processor activate selected control signals in the information bus interface which causes the stored address to be modified in response to the control signals. This feature is useful to read a new instruction from external memory without the requirement of a new transmission of program instruction address every time a new instruction is fetched by the processor.

REFERENCES:
patent: 4161788 (1979-07-01), Rosenblum
patent: 4286321 (1981-08-01), Baker et al.

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