Quadruply extended time multiplexed information bus for reducing

Details Quadruply extended time multiplexed information bus for reducing Quadruply extended time multiplexed information bus for reducing

1981-10-01

1989-03-07

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 100

Patent

active

048112020

ABSTRACT:
A digital processor system includes a processor, a memory and a memory interface between the processor and the memory. The memory stores data in one bit format but addresses the data in a second bit format. The interface to the memory includes a controller that is responsive to the processor, an information bus for the transfer of addresses and data and two registers to store addresses for the memory. These registers in the interface are responsive to the processor through the interface controls in order to allow the processor to increment or decrement the memory addresses or load new memory addresses from the information bus. These registers are then connected to a switch which is in turn responsive to the processor through the interface control in order that the processor can determine which register is to provide the address to the memory.

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Brown et al., "Instructions for Byte Addressing Capability", IBM Tech. Dis. Bull., vol. 16, No. 3, Aug. 1973, pp. 812-815.

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