Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
1999-10-07
2003-11-18
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C375S235000
Reexamination Certificate
active
06650264
ABSTRACT:
This application is related to the following U.S. patent applications that have been previously filed on Mar. 10, 1999, and that are hereby incorporated by reference in their entirety: Ser. No. 09/265,663, entitled “Method and Apparatus for Demodulation of Radio Data Signals” by Eric J. King and Brian D. Green.; Ser. No. 09/266,418, entitled “Station Scan Method and Apparatus for Radio Receivers” by James M. Nohrden and Brian P. Lum Shue Chan; Ser. No. 09/265,659, entitled “Method and Apparatus for Discriminating Multipath and Pulse Noise Distortions in Radio Receivers” by James M. Nohrden, Brian D. Green and Brian P. Lum Shue Chan; Ser. No. 09/265,752, entitled “Digital Stereo Recovery Circuitry and Method For Radio Receivers” by Brian D. Green; and Ser. No. 09/265,758, entitled “Complex Bandpass Modulator and Method for Analog-to-Digital Converters” by Brian D. Green.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to sampling architectures for analog-to-digital converters. More specifically, the present invention relates to techniques for providing complex sampled values for delta-sigma analog-to-digital converters.
2. Description of the Related Art
Many devices utilize analog-to-digital converters (ADCs) to convert analog information to digital information so that signal processing may be accomplished on the digital side. An intermediate frequency (IF) digital receiver within an AM/FM radio is one example of a device that has a use for such an ADC. In particular, delta-sigma ADCs are useful in providing digital information that may be further processed by digital signal processing. The signals processed by a delta-sigma ADC are often complex signals including both an in-phase (real) and a quadrature (imaginary) signal data paths. In such signal processing systems, the complex input signals are typically sampled at some desired sampling frequency to ultimately produce a real digital data stream and an imaginary digital data stream.
The traditional architecture for generating sampled complex signals includes quadrature mixing followed by filter circuitry and sampling circuitry. Quadrature mixing is performed to break the input signal into a real path signal and an imaginary path signal. To generate the real path or in-phase signal, the input signal is mixed with a selected mixing signal. To generate the imaginary or quadrature path signal, the input signal is mixed with the same mixing signal shifted in phase by 90 degrees. This mixing operation, however, tends to introduce undesirable two-times (2×) images into the real and imaginary path signals. To eliminate these 2× images, filter circuitry, such as low pass filters, is often added to both the real and imaginary signal paths. Such filters may also provide some anti-aliasing for the analog-to-digital sampling. The real and imaginary signals are then sampled at the same sampling frequency to generate real and imaginary digital data streams. This traditional quadrature mixing sampling architecture suffers from various problems, including complexity and large size requirements, the introduction of undesired artifacts into the real and imaginary signal paths, and magnitude distortion of the real and imaginary signals at baseband.
SUMMARY OF THE INVENTION
In accordance with the present invention, quadrature sampling architecture and an associated method provide improved output signals over prior quadrature mixing implementations. Sampling circuitry according to the present invention samples an input signal with a first and second sampling signals to directly produce real and imaginary sampled output signals. The first sampling signal, which is associated with the real sampled output signal, is delayed by one-fourth cycle with respect to the second sampling signal, which is associated with the imaginary sampled output signal. This one-fourth cycle sampling signal difference allows for simplified construction of the sampling circuitry. In addition, filter circuitry according to the present invention processes the real and imaginary digital data output signals so that the imaginary digital data output signal is advanced by one-fourth cycle with respect to the real digital data output signal. This one-fourth cycle relative advance tends to eliminate undesirable magnitude distortion and errors in the digital output signals at baseband. Furthermore, the real and imaginary signal paths may be interchanged and still take advantage of the present invention.
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Chan Brian P. Lum Shue
Green Brian D.
Kerth Donald A.
Cirrus Logic Inc.
Lin, Esq. Steven
Wamsley Patrick
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