Quadrature receiver sampling architecture

Details Quadrature receiver sampling architecture Quadrature receiver sampling architecture

2006-11-21

2006-11-21

Corrielus, Jean B. (Department: 2611)

Pulse or digital communications

Receivers

C375S350000, C455S003020

Reexamination Certificate

active

07139332

ABSTRACT:
Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.

REFERENCES:
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patent: 5506862 (1996-04-01), McIntosh
patent: 5550869 (1996-08-01), Gurantz et al.
patent: 6329939 (2001-12-01), Swaminathan et al.
patent: 2003/0142639 (2003-07-01), Cheung et al.
patent: 2003/0186666 (2003-10-01), Sindhushayana
patent: 2005/0114904 (2005-05-01), Monk et al.

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