Quadrature divider

Details Quadrature divider Quadrature divider

2006-07-06

2008-09-16

Richards, N. Drew (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S115000

Reexamination Certificate

active

07425850

ABSTRACT:
The quadrature divider comprises a plurality of flip-flops, including at least a first flip flop and an endmost flip-flop, interoperably coupled in series to produce a predetermined dividing ratio, wherein each of the plurality of flip-flops includes differential inputs, differential outputs and differential clock inputs, the outputs of one flip-flop are connected to the corresponding inputs of a subsequent flip-flop, the outputs of the endmost flip-flop are connected inversely to the inputs of the first flip-flop, wherein the flip-flops are clocked at their clock inputs with differential clock signals in a consecutive manner which, for each flip-flop and depending on the dividing ratio, are individually selected from quadrature clock input signals.

REFERENCES:
patent: 6583674 (2003-06-01), Melava et al.
patent: 6831489 (2004-12-01), Cheung et al.
patent: 7095353 (2006-08-01), Sander et al.
patent: 7298183 (2007-11-01), Mirzaei et al.
patent: 2002/0039894 (2002-04-01), Yoshida et al.
patent: 2007/0024329 (2007-02-01), Heidari et al.
Yang, Lixin, et al.: “A Non-Feedback Multiphase Clock Generator”, IEEE International Symposium on Circuits and Systems, ISCAS 2002.

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