Quadrature demodulator with phase-locked loop

Details Quadrature demodulator with phase-locked loop Quadrature demodulator with phase-locked loop

2000-12-07

2002-10-15

Kinkead, Arnold (Department: 2817)

Demodulators

Phase shift keying or quadrature amplitude demodulator

Input signal combined with local oscillator or carrier...

C455S258000, C455S259000, C455S260000, C329S305000, C329S325000, C329S304000, C375S324000, C375S327000

Reexamination Certificate

active

06466086

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a quadrature demodulator equipped with a Phase-Locked Loop (PLL) and more particularly, to a quadrature demodulator equipped with a PLL section for stabilizing the oscillation frequency of the oscillator for the carrier frequency, which is applicable to digital communication and/or digital broadcast.
2. Description of the Related Art
With digital communication and digital broadcast, the system of Quadrature Phase Shift Keying (QPSK) is often used. QPSK is one of digital modulation systems, which is explained below.
With the QPSK system, the baseband signal containing the information to be transmitted is mixed with two carrier signals having the same frequency and a phase difference of 90° (i.e., two orthogonal carrier signals) in frequency mixers, generating two orthogonal modulated signals. These two modulated signals, which are Binary PSK (BPSK) signals, are termed the “in-phase modulated signal” (i.e., I-modulated signal) and the “quadrature-phase modulated signal” (i.e., Q-modulated signal). The I- and Q-modulated signals thus generated are added or synthesized together by an adder, forming the QPSK modulated signal.
To demodulate the QPSK modulated signal, two carrier signals having the same frequency as the QPSK modulated signal and a phase difference of 90° to each other are generated in a receiver, thereby generating two orthogonal carrier signals. The QPSK modulated signal is mixed with the two orthogonal carrier signals thus generated by frequency mixers in the receiver, thereby forming two orthogonal BPSK demodulated signals (i.e., an “I-demodulated signal” and a “Q-demodulated signal”). The I- and Q-demodulated signals thus formed are demodulated by a detector in the receiver according to the specified detection method (e.g., delayed detection or synchronous detection) Thus, the baseband signal containing the information to be transmitted is reproduced.
On the other hand, with digital mobile telephones and satellite broadcasting receivers, the double conversion method is usually used. With the double conversion method, the Radio-Frequency (RF) received signal is converted into an Intermediate-Frequency (IF) signal. Next, unnecessary signals contained in the IF signal are removed and then, the IF signal is converted into the baseband signal. Thus, the information in the baseband signal is reproduced in the receiver side.
Various types of quadrature demodulators have ever been developed for digital mobile telephones and satellite broadcasting receivers to demodulate the QPSK modulated signal according to the Double Conversion method. An example of the quadrature demodulators is shown in
FIG. 1
, which is designed for receiving the signal from the Direct Broadcast Satellite (DBS).
As seen from
FIG. 1
, the prior-art quadrature demodulator comprises a quadrature demodulator section
110
, an oscillator
120
, a PLL section
130
, and a resonant circuit
140
. The demodulator section
110
, the oscillator
120
, and the PLL section
130
are provided on the Integrated Circuit (IC)
101
of the quadrature demodulator. The resonant circuit
140
is provided outside the IC
101
.
An input IF signal S
IF
with a specific intermediate frequency (e.g., 480±30 MHz) is inputted into the input terminal T
IN
of the prior-art quadrature demodulator. The input signal S
IF
thus inputted is sent to the quadrature demodulator section
110
on the IC
101
by way of a capacitor C
11
and a terminal T
1
.
In the quadrature demodulator section
110
, an IF amplifier
111
amplifies the input signal S
IF
to generate an amplified IF signal S
IFA
. The IF signal S
IFA
thus generated is sent to an I-signal mixer
112
and a Q-signal mixer
114
. The I-signal mixer
112
frequency-converts the IF signal S
IFA
to generate a baseband I signal S
BI
. The, Q-signal mixer
114
frequency-converts the IF signal S
IFA
to generate a baseband Q signal S
BQ
.
Specifically, the quadrature demodulator section
110
comprises a frequency multiplier
117
and a 90°-phase shifter
116
. The frequency multiplier
117
doubles a local frequency f
LOC
(e.g., 479.5 MHz) of a local signal (i.e., the carrier signal) sent from the oscillator
120
, forming a signal S
LOC2
with a doubled frequency 2f
LOC
(e.g., 959 MHz). The 90° phase shifter
116
frequency-divides the signal S
LOC2
thus formed and phase-shifts the same by 90°, generating a local I signal S
LOCI
with the frequency f
LOC
and a local Q signal S
LOCQ
with the same frequency f
LOC
. Then, the phase shifter
116
sends the local I signal S
LOCI
with the 0°-phase to an I signal mixer
112
and the local Q signal S
LOCQ
with the 90° phase to a Q signal mixer
114
.
The I signal mixer
112
mixes the amplified IF signal S
IFA
sent from the IF amplifier
111
with the local I signal S
LOCI
sent from the phase shifter
116
, generating a baseband I signal S
BI
with the 0°-phase. Similarly, the Q signal mixer
114
mixes the amplified IF signal S
IFA
sent from the IF amplifier
111
with the local Q signal S
LOCQ
sent from the phase shifter
116
, generating a baseband Q signal S
BQ
with the 90° phase. The baseband I and Q signals S
BI
and S
BQ
have the same frequency (e.g., 30 MHz).
Baseband amplifiers
113
and
115
amplify the baseband I and Q signals S
BI
and S
BQ
, thereby producing amplified baseband I and Q signals S
BIA
and S
BQA
, respectively. The amplified baseband I and Q signals S
BIA
and S
BQA
thus produced are outputted from the IC
101
by way of its terminals T
2
and T
3
, respectively. Then, the amplified baseband I and Q signals S
BIA
and S
BQA
are further outputted from the output terminals T
OUT1
and T
OUT2
of the prior-art quadrature demodulator by way of capacitors C
12
and C
13
as the baseband output I and Q signals S
BIO
and S
BQO
, respectively. The baseband output I and Q signals S
BIO
and S
BQO
thus outputted are sent to a detector (not shown) in a next stage.
The oscillator
120
and the resonant circuit
140
cooperate to generate the local signal S
LOC
with the specified local frequency f
LOC
. The oscillation frequency of the oscillator
120
, which is equal to the local frequency f
LOC
, can be set and varied by adjusting the resonant frequency of the resonant circuit
140
.
The resonant circuit
140
, which is located outside the demodulator IC
101
, comprises a varactor diode BD capable of changing its capacitance according to an applied voltage, an inductor L
11
, and six capacitors C
14
, C
15
, C
16
, C
17
, C
18
, and C
19
. A resistor R
11
, which is connected between the varactor diode BD and a terminal T
9
of the IC
101
, serves to prevent excess currents from flowing through the diode BD. Similarly, a resistor R
12
, which is connected between the varactor diode BD and the ground, serves to prevent excess currents from flowing through the diode BD. The resonant circuit
140
having such a configuration is connected to the oscillator
120
by way of four terminals T
5
, T
6
, T
7
, and T
8
of the IC
101
.
The PLL section
130
comprises a prescaler
131
, a counter
132
, a frequency divider
133
, a phase comparator
134
, a charge pump
135
, and a Direct Current (DC) amplifier
136
. The PLL section
130
compares the local frequency f
LOC
of the local signal S
LOC
with the reference frequency f
REF
of a reference signal S
REF
produced by a quartz oscillator X
11
, thereby stabilizing the local frequency f
LOC
against the change in the power supply voltage and the ambient temperature. The quartz oscillator X
11
is provided outside the IC
101
and connected to its terminal T
4
.
The prescaler
131
serves as a frequency divider for dividing an incoming frequency by N
1
, where N
1
is a positive constant. The prescaler
131
receives the local signal S
LOC
sent from the oscillator
120
and produces a signal S
PS
with a divided frequency (f
LOC
/N
1
) The
The counter
132
serves as a frequency divider for dividing an incoming frequency by N
2
, where N
2
is a positi

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