Quad flat non-leaded package and manufacturing method thereof

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support

Reexamination Certificate

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Details

C438S112000, C438S127000, C438S617000, C257SE21509, C257SE23024

Reexamination Certificate

active

07993982

ABSTRACT:
A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.

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patent: 2009/0140411 (2009-06-01), Masuda et al.

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