Quad flat no-lead chip carrier with stand-off

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices

Reexamination Certificate

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C438S112000, C438S121000

Reexamination Certificate

active

07405106

ABSTRACT:
A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved. As a result of the improved die paddle solder joint area coverage, improved thermal performance of the chip carrier is also significantly improved.

REFERENCES:
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patent: 5920116 (1999-07-01), Umehara et al.
patent: 6621152 (2003-09-01), Choi et al.
patent: 6861734 (2005-03-01), Minamio et al.
patent: 6882057 (2005-04-01), Hsu
patent: 6897550 (2005-05-01), Zwenger et al.
patent: 7122406 (2006-10-01), Yilmaz et al.
patent: 2003/0006055 (2003-01-01), Chien-Hung et al.
patent: 2003/0178708 (2003-09-01), Minamio et al.

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