Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
2005-04-19
2005-04-19
Parekh, Nitin (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S774000, C257S787000, C257S676000, C257S666000, C257S712000, C257S713000
Reexamination Certificate
active
06882057
ABSTRACT:
A quad flat no-lead chip carrier for a wire-bonded chip package is provided. The chip carrier comprises a conductive plate, a plurality of conductive columns and a plurality of dielectric walls. A chip is attached to the conductive plate. The conductive plate furthermore has a plurality of columnar through holes distributed around a chip-bonding region. The conductive columns are set up within the columnar through holes. The dielectric walls are set up between the sidewall of the conductive columns and the inner surface of the columnar through holes. The chip is electrically connected to the conductive columns via conductive wires. The bottom end of the conductive columns serves as input/output contacts for connecting with external contacts. The chip carrier is able to increase overall density of the input/output contacts and improve the electrical performance of the chip package.
REFERENCES:
patent: 5122860 (1992-06-01), Kikuchi et al.
patent: 6400010 (2002-06-01), Murata
patent: 20030151139 (2003-08-01), Kimura
Jiang Chyun IP Office
Parekh Nitin
VIA Technologies Inc.
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