Pyramid learning architecture neurocomputer

Details Pyramid learning architecture neurocomputer Pyramid learning architecture neurocomputer

1993-06-18

1994-06-28

MacDonald, Allen R.

395 11, 395800, G06F 1500

Patent

active

053254643

ABSTRACT:
The Pyramid Learning Architecture Neurocomputer (PLAN) is a scalable stacked pyramid arrangement of processor arrays. There are six processing levels in PLAN consisting of the pyramid base, Level 6, containing N.sup.2 SYnapse Processors (SYPs), Level 5 containing multiple folded Communicating Adder Tree structures (SCATs), Level 4 made up of N completely connected Neuron Execution Processors (NEPs), Level 3 made up of multiple Programmable Communicating Alu Tree (PCATs) structures, similar to Level 5 SCATs but with programmable function capabilities in each tree node, Level 2 containing the Neuron Instruction Processor (NIP), and Level 1 comprising the Host and user interface. The simplest processors are in the base level with each layer of processors increasing in computational power up to a general purpose host computer acting as the user interface. PLAN is scalable in direct neural network emulation and in virtual processing capability. Consequently, depending upon performance and cost trade-offs, the number of physical neurons N to be implemented is chosen. A neural network model is mapped onto Level 3 PCATs, Level 4 NEPs, Level 5 SCATs, and Level 6 SYPs. The Neuron Instruction Processor, Level 2, controls the neural network model through the Level 3 programmable interconnection interface. In addition, the NIP level controls the high speed and high capacity PLAN I/O interface necessary for large N massively parallel systems. This discussion describes the PLAN processors attached to a Host computer and the overall control of the pyramid which constitutes the neurocomputer system.

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